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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3412-drm-amd-display-enabling-seamless-boot-sequence-for-.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3412-drm-amd-display-enabling-seamless-boot-sequence-for-.patch521
1 files changed, 521 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3412-drm-amd-display-enabling-seamless-boot-sequence-for-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3412-drm-amd-display-enabling-seamless-boot-sequence-for-.patch
new file mode 100644
index 00000000..c91df5fa
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3412-drm-amd-display-enabling-seamless-boot-sequence-for-.patch
@@ -0,0 +1,521 @@
+From 5f3077c37a139b6fda265aa32fe5cb9d43414c61 Mon Sep 17 00:00:00 2001
+From: Martin Leung <martin.leung@amd.com>
+Date: Wed, 17 Jul 2019 16:08:19 -0400
+Subject: [PATCH 3412/4256] drm/amd/display: enabling seamless boot sequence
+ for dcn2
+
+[Why]
+Seamless boot (building SW state inheriting BIOS-initialized timing) was
+enabled on DCN2, including fixes
+
+[How]
+Includes fixes for MPC, DPPCLK, and DIG FE mapping/OTG source select/
+Pixel clock.
+
+This is part 2 of 2 for seamless boot NV10
+
+Signed-off-by: Martin Leung <martin.leung@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 26 +++++++---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 13 ++++-
+ .../gpu/drm/amd/display/dc/core/dc_resource.c | 39 +++++++++------
+ .../drm/amd/display/dc/dce/dce_clock_source.c | 3 +-
+ .../amd/display/dc/dce/dce_stream_encoder.c | 12 +++++
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 13 +++--
+ .../amd/display/dc/dcn10/dcn10_link_encoder.c | 49 +++++++++++++++----
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 19 +++++++
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h | 4 ++
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.h | 4 ++
+ .../display/dc/dcn10/dcn10_stream_encoder.c | 12 +++++
+ .../display/dc/dcn10/dcn10_stream_encoder.h | 3 ++
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c | 1 +
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 3 +-
+ .../display/dc/dcn20/dcn20_stream_encoder.c | 1 +
+ drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 3 ++
+ .../amd/display/dc/inc/hw/stream_encoder.h | 3 ++
+ 17 files changed, 172 insertions(+), 36 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 409d9a02f613..3e79bdbc68e9 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -969,7 +969,7 @@ bool dc_validate_seamless_boot_timing(const struct dc *dc,
+ {
+ struct timing_generator *tg;
+ struct dc_link *link = sink->link;
+- unsigned int inst;
++ unsigned int enc_inst, tg_inst;
+
+ /* Check for enabled DIG to identify enabled display */
+ if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
+@@ -981,13 +981,22 @@ bool dc_validate_seamless_boot_timing(const struct dc *dc,
+ * current implementation always map 1-to-1, so this code makes
+ * the same assumption and doesn't check OTG source.
+ */
+- inst = link->link_enc->funcs->get_dig_frontend(link->link_enc) - 1;
++ enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
+
+ /* Instance should be within the range of the pool */
+- if (inst >= dc->res_pool->pipe_count)
++ if (enc_inst >= dc->res_pool->pipe_count)
+ return false;
+
+- tg = dc->res_pool->timing_generators[inst];
++ if (enc_inst >= dc->res_pool->stream_enc_count)
++ return false;
++
++ tg_inst = dc->res_pool->stream_enc[enc_inst]->funcs->dig_source_otg(
++ dc->res_pool->stream_enc[enc_inst]);
++
++ if (tg_inst >= dc->res_pool->timing_generator_count)
++ return false;
++
++ tg = dc->res_pool->timing_generators[tg_inst];
+
+ if (!tg->funcs->is_matching_timing)
+ return false;
+@@ -1000,10 +1009,11 @@ bool dc_validate_seamless_boot_timing(const struct dc *dc,
+
+ dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
+ dc->res_pool->dp_clock_source,
+- inst, &pix_clk_100hz);
++ tg_inst, &pix_clk_100hz);
+
+ if (crtc_timing->pix_clk_100hz != pix_clk_100hz)
+ return false;
++
+ }
+
+ return true;
+@@ -1913,13 +1923,17 @@ static void commit_planes_do_stream_update(struct dc *dc,
+
+ if (stream_update->dpms_off) {
+ dc->hwss.pipe_control_lock(dc, pipe_ctx, true);
++
+ if (*stream_update->dpms_off) {
+ core_link_disable_stream(pipe_ctx, KEEP_ACQUIRED_RESOURCE);
+ dc->hwss.optimize_bandwidth(dc, dc->current_state);
+ } else {
+- dc->hwss.prepare_bandwidth(dc, dc->current_state);
++ if (!dc->optimize_seamless_boot)
++ dc->hwss.prepare_bandwidth(dc, dc->current_state);
++
+ core_link_enable_stream(dc->current_state, pipe_ctx);
+ }
++
+ dc->hwss.pipe_control_lock(dc, pipe_ctx, false);
+ }
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index ed8bdcf44c8e..9fe324dbbe91 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -1419,6 +1419,16 @@ static enum dc_status enable_link_dp(
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ bool fec_enable;
+ #endif
++ int i;
++ bool apply_seamless_boot_optimization = false;
++
++ // check for seamless boot
++ for (i = 0; i < state->stream_count; i++) {
++ if (state->streams[i]->apply_seamless_boot_optimization) {
++ apply_seamless_boot_optimization = true;
++ break;
++ }
++ }
+
+ /* get link settings for video mode timing */
+ decide_link_settings(stream, &link_settings);
+@@ -1440,7 +1450,8 @@ static enum dc_status enable_link_dp(
+
+ pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
+ link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
+- state->clk_mgr->funcs->update_clocks(state->clk_mgr, state, false);
++ if (!apply_seamless_boot_optimization)
++ state->clk_mgr->funcs->update_clocks(state->clk_mgr, state, false);
+
+ dp_enable_link_phy(
+ link,
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+index 5f2f2c7e7445..fa94dfc04dce 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+@@ -1890,7 +1890,7 @@ static int acquire_resource_from_hw_enabled_state(
+ struct dc_stream_state *stream)
+ {
+ struct dc_link *link = stream->link;
+- unsigned int inst;
++ unsigned int inst, tg_inst;
+
+ /* Check for enabled DIG to identify enabled display */
+ if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
+@@ -1902,28 +1902,37 @@ static int acquire_resource_from_hw_enabled_state(
+ * current implementation always map 1-to-1, so this code makes
+ * the same assumption and doesn't check OTG source.
+ */
+- inst = link->link_enc->funcs->get_dig_frontend(link->link_enc) - 1;
++ inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
+
+ /* Instance should be within the range of the pool */
+ if (inst >= pool->pipe_count)
+ return -1;
+
+- if (!res_ctx->pipe_ctx[inst].stream) {
+- struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[inst];
++ if (inst >= pool->stream_enc_count)
++ return -1;
++
++ tg_inst = pool->stream_enc[inst]->funcs->dig_source_otg(pool->stream_enc[inst]);
++
++ if (tg_inst >= pool->timing_generator_count)
++ return false;
++
++ if (!res_ctx->pipe_ctx[tg_inst].stream) {
++ struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst];
++
++ pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
++ pipe_ctx->plane_res.mi = pool->mis[tg_inst];
++ pipe_ctx->plane_res.hubp = pool->hubps[tg_inst];
++ pipe_ctx->plane_res.ipp = pool->ipps[tg_inst];
++ pipe_ctx->plane_res.xfm = pool->transforms[tg_inst];
++ pipe_ctx->plane_res.dpp = pool->dpps[tg_inst];
++ pipe_ctx->stream_res.opp = pool->opps[tg_inst];
+
+- pipe_ctx->stream_res.tg = pool->timing_generators[inst];
+- pipe_ctx->plane_res.mi = pool->mis[inst];
+- pipe_ctx->plane_res.hubp = pool->hubps[inst];
+- pipe_ctx->plane_res.ipp = pool->ipps[inst];
+- pipe_ctx->plane_res.xfm = pool->transforms[inst];
+- pipe_ctx->plane_res.dpp = pool->dpps[inst];
+- pipe_ctx->stream_res.opp = pool->opps[inst];
+- if (pool->dpps[inst])
+- pipe_ctx->plane_res.mpcc_inst = pool->dpps[inst]->inst;
+- pipe_ctx->pipe_idx = inst;
++ if (pool->dpps[tg_inst])
++ pipe_ctx->plane_res.mpcc_inst = pool->dpps[tg_inst]->inst;
++ pipe_ctx->pipe_idx = tg_inst;
+
+ pipe_ctx->stream = stream;
+- return inst;
++ return tg_inst;
+ }
+
+ return -1;
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+index 464d7c3830ef..990481b35682 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+@@ -1059,7 +1059,8 @@ static bool dcn20_program_pix_clk(
+ static const struct clock_source_funcs dcn20_clk_src_funcs = {
+ .cs_power_down = dce110_clock_source_power_down,
+ .program_pix_clk = dcn20_program_pix_clk,
+- .get_pix_clk_dividers = dce112_get_pix_clk_dividers
++ .get_pix_clk_dividers = dce112_get_pix_clk_dividers,
++ .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz
+ };
+ #endif
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
+index 7e8b8ae036ee..9205fb2e08bd 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
+@@ -1600,6 +1600,17 @@ static void dig_connect_to_otg(
+ REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst);
+ }
+
++static unsigned int dig_source_otg(
++ struct stream_encoder *enc)
++{
++ uint32_t tg_inst = 0;
++ struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
++
++ REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst);
++
++ return tg_inst;
++}
++
+ static const struct stream_encoder_funcs dce110_str_enc_funcs = {
+ .dp_set_stream_attribute =
+ dce110_stream_encoder_dp_set_stream_attribute,
+@@ -1635,6 +1646,7 @@ static const struct stream_encoder_funcs dce110_str_enc_funcs = {
+ .set_avmute = dce110_stream_encoder_set_avmute,
+ .dig_connect_to_otg = dig_connect_to_otg,
+ .hdmi_reset_stream_attribute = dce110_reset_hdmi_stream_attribute,
++ .dig_source_otg = dig_source_otg,
+ };
+
+ void dce110_stream_encoder_construct(
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 167bd6e92afa..86f874bddd84 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -1097,9 +1097,16 @@ static void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
+ }
+ }
+
+- /* Cannot reset the MPC mux if seamless boot */
+- if (!can_apply_seamless_boot)
+- dc->res_pool->mpc->funcs->mpc_init(dc->res_pool->mpc);
++ for (i = 0; i < dc->res_pool->pipe_count; i++) {
++ struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
++
++ /* Cannot reset the MPC mux if seamless boot */
++ if (pipe_ctx->stream != NULL && can_apply_seamless_boot)
++ continue;
++
++ dc->res_pool->mpc->funcs->mpc_init_single_inst(
++ dc->res_pool->mpc, i);
++ }
+
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct timing_generator *tg = dc->res_pool->timing_generators[i];
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
+index 9427a461bb26..e4c7ecd87de7 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
+@@ -443,6 +443,46 @@ static uint8_t get_frontend_source(
+ }
+ }
+
++unsigned int dcn10_get_dig_frontend(struct link_encoder *enc)
++{
++ struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
++ int32_t value;
++ enum engine_id result;
++
++ REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &value);
++
++ switch (value) {
++ case DCN10_DIG_FE_SOURCE_SELECT_DIGA:
++ result = ENGINE_ID_DIGA;
++ break;
++ case DCN10_DIG_FE_SOURCE_SELECT_DIGB:
++ result = ENGINE_ID_DIGB;
++ break;
++ case DCN10_DIG_FE_SOURCE_SELECT_DIGC:
++ result = ENGINE_ID_DIGC;
++ break;
++ case DCN10_DIG_FE_SOURCE_SELECT_DIGD:
++ result = ENGINE_ID_DIGD;
++ break;
++ case DCN10_DIG_FE_SOURCE_SELECT_DIGE:
++ result = ENGINE_ID_DIGE;
++ break;
++ case DCN10_DIG_FE_SOURCE_SELECT_DIGF:
++ result = ENGINE_ID_DIGF;
++ break;
++ case DCN10_DIG_FE_SOURCE_SELECT_DIGG:
++ result = ENGINE_ID_DIGG;
++ break;
++ default:
++ // invalid source select DIG
++ ASSERT(false);
++ result = ENGINE_ID_UNKNOWN;
++ }
++
++ return result;
++
++}
++
+ void enc1_configure_encoder(
+ struct dcn10_link_encoder *enc10,
+ const struct dc_link_settings *link_settings)
+@@ -498,15 +538,6 @@ bool dcn10_is_dig_enabled(struct link_encoder *enc)
+ return value;
+ }
+
+-unsigned int dcn10_get_dig_frontend(struct link_encoder *enc)
+-{
+- struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+- uint32_t value;
+-
+- REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &value);
+- return value;
+-}
+-
+ static void link_encoder_disable(struct dcn10_link_encoder *enc10)
+ {
+ /* reset training pattern */
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
+index 4f7a10390c57..8b2f29f6dabd 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
+@@ -364,6 +364,24 @@ void mpc1_mpc_init(struct mpc *mpc)
+ }
+ }
+
++void mpc1_mpc_init_single_inst(struct mpc *mpc, unsigned int mpcc_id)
++{
++ struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
++ int opp_id;
++
++ REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id);
++
++ REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);
++ REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
++ REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf);
++
++ mpc1_init_mpcc(&(mpc->mpcc_array[mpcc_id]), mpcc_id);
++
++ if (opp_id < MAX_OPP && REG(MUX[opp_id]))
++ REG_UPDATE(MUX[opp_id], MPC_OUT_MUX, 0xf);
++}
++
++
+ void mpc1_init_mpcc_list_from_hw(
+ struct mpc *mpc,
+ struct mpc_tree *tree)
+@@ -433,6 +451,7 @@ static const struct mpc_funcs dcn10_mpc_funcs = {
+ .insert_plane = mpc1_insert_plane,
+ .remove_mpcc = mpc1_remove_mpcc,
+ .mpc_init = mpc1_mpc_init,
++ .mpc_init_single_inst = mpc1_mpc_init_single_inst,
+ .get_mpcc_for_dpp = mpc1_get_mpcc_for_dpp,
+ .wait_for_idle = mpc1_assert_idle_mpcc,
+ .assert_mpcc_idle_before_connect = mpc1_assert_mpcc_idle_before_connect,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
+index d3d16c4cbea3..962a68e322ee 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
+@@ -149,6 +149,10 @@ void mpc1_remove_mpcc(
+ void mpc1_mpc_init(
+ struct mpc *mpc);
+
++void mpc1_mpc_init_single_inst(
++ struct mpc *mpc,
++ unsigned int mpcc_id);
++
+ void mpc1_assert_idle_mpcc(
+ struct mpc *mpc,
+ int id);
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+index 02599eb92ca6..66c08d05da0e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+@@ -539,6 +539,10 @@ struct dcn_otg_state {
+ void optc1_read_otg_state(struct optc *optc1,
+ struct dcn_otg_state *s);
+
++bool optc1_is_matching_timing(
++ struct timing_generator *tg,
++ const struct dc_crtc_timing *otg_timing);
++
+ bool optc1_validate_timing(
+ struct timing_generator *optc,
+ const struct dc_crtc_timing *timing);
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+index 00aa9dde5538..6800b906a86e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+@@ -1541,6 +1541,17 @@ void enc1_dig_connect_to_otg(
+ REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst);
+ }
+
++unsigned int enc1_dig_source_otg(
++ struct stream_encoder *enc)
++{
++ uint32_t tg_inst = 0;
++ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
++
++ REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst);
++
++ return tg_inst;
++}
++
+ static const struct stream_encoder_funcs dcn10_str_enc_funcs = {
+ .dp_set_stream_attribute =
+ enc1_stream_encoder_dp_set_stream_attribute,
+@@ -1576,6 +1587,7 @@ static const struct stream_encoder_funcs dcn10_str_enc_funcs = {
+ .set_avmute = enc1_stream_encoder_set_avmute,
+ .dig_connect_to_otg = enc1_dig_connect_to_otg,
+ .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute,
++ .dig_source_otg = enc1_dig_source_otg,
+ };
+
+ void dcn10_stream_encoder_construct(
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+index 8b8921e75984..a512cbea00d1 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+@@ -598,6 +598,9 @@ void enc1_dig_connect_to_otg(
+ struct stream_encoder *enc,
+ int tg_inst);
+
++unsigned int enc1_dig_source_otg(
++ struct stream_encoder *enc);
++
+ void enc1_stream_encoder_set_stream_attribute_helper(
+ struct dcn10_stream_encoder *enc1,
+ struct dc_crtc_timing *crtc_timing);
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
+index 67f0128f0b38..17950d9e53cf 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
+@@ -498,6 +498,7 @@ const struct mpc_funcs dcn20_mpc_funcs = {
+ .insert_plane = mpc1_insert_plane,
+ .remove_mpcc = mpc1_remove_mpcc,
+ .mpc_init = mpc1_mpc_init,
++ .mpc_init_single_inst = mpc1_mpc_init_single_inst,
+ .update_blending = mpc2_update_blending,
+ .get_mpcc_for_dpp = mpc2_get_mpcc_for_dpp,
+ .wait_for_idle = mpc2_assert_idle_mpcc,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+index 1ae973962d53..6dede495d0fd 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+@@ -522,7 +522,8 @@ static struct timing_generator_funcs dcn20_tg_funcs = {
+ .set_gsl_source_select = optc2_set_gsl_source_select,
+ .set_vtg_params = optc1_set_vtg_params,
+ .program_manual_trigger = optc2_program_manual_trigger,
+- .setup_manual_trigger = optc2_setup_manual_trigger
++ .setup_manual_trigger = optc2_setup_manual_trigger,
++ .is_matching_timing = optc1_is_matching_timing
+ };
+
+ void dcn20_timing_generator_init(struct optc *optc1)
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+index b2c1cad3c94f..a2f15387e946 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+@@ -578,6 +578,7 @@ static const struct stream_encoder_funcs dcn20_str_enc_funcs = {
+ .setup_stereo_sync = enc1_setup_stereo_sync,
+ .set_avmute = enc1_stream_encoder_set_avmute,
+ .dig_connect_to_otg = enc1_dig_connect_to_otg,
++ .dig_source_otg = enc1_dig_source_otg,
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ .enc_read_state = enc2_read_state,
+ #endif
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
+index 9f00289bda78..9dde88d4571c 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
+@@ -199,6 +199,9 @@ struct mpc_funcs {
+ * Return: void
+ */
+ void (*mpc_init)(struct mpc *mpc);
++ void (*mpc_init_single_inst)(
++ struct mpc *mpc,
++ unsigned int mpcc_id);
+
+ /*
+ * Update the blending configuration for a specified MPCC.
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
+index 38e2c3e7412e..067ba6fc04c1 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
+@@ -214,6 +214,9 @@ struct stream_encoder_funcs {
+ void (*hdmi_reset_stream_attribute)(
+ struct stream_encoder *enc);
+
++ unsigned int (*dig_source_otg)(
++ struct stream_encoder *enc);
++
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ void (*dp_set_dsc_config)(
+--
+2.17.1
+
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-04-24 21:56:27 +0000