1 files changed, 63 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3411-drm-amd-display-fix-dcn-specific-clk_mgr-init_clocks.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3411-drm-amd-display-fix-dcn-specific-clk_mgr-init_clocks.patch
new file mode 100644
index 00000000..85dfa045
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3411-drm-amd-display-fix-dcn-specific-clk_mgr-init_clocks.patch
@@ -0,0 +1,63 @@
+From 234148db1b2013476a71e751e99471d8da621871 Mon Sep 17 00:00:00 2001
+From: Martin Leung <martin.leung@amd.com>
+Date: Sun, 28 Jul 2019 11:09:11 -0400
+Subject: [PATCH 3411/4256] drm/amd/display: fix dcn-specific clk_mgr
+ init_clocks
+
+[Why]
+underflow seen on certain monitor setups caused by making dcnxx_init_hw
+generic
+
+[How]
+by moving dcn20_init_hw into dcn10, we added a dcn-specific clk_mgr
+init (dc->clk_mgr->funcs->init_clocks()). Thus, put old clk_mgr
+memset in an else statement so both memsets don't get set
+
+Signed-off-by: Martin Leung <martin.leung@amd.com>
+Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c | 6 ++++++
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 2 --
+ 2 files changed, 6 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
+index ad1478378f16..d00ee9fa04e4 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
+@@ -31,6 +31,11 @@
+ #include "rv1_clk_mgr_vbios_smu.h"
+ #include "rv1_clk_mgr_clk.h"
+ 
++void rv1_init_clocks(struct clk_mgr *clk_mgr)
++{
++	memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
++}
++
+ static int rv1_determine_dppclk_threshold(struct clk_mgr_internal *clk_mgr, struct dc_clocks *new_clocks)
+ {
+ 	bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz;
+@@ -234,6 +239,7 @@ static void rv1_enable_pme_wa(struct clk_mgr *clk_mgr_base)
+ }
+ 
+ static struct clk_mgr_funcs rv1_clk_funcs = {
++	.init_clocks = rv1_init_clocks,
+ 	.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
+ 	.update_clocks = rv1_update_clocks,
+ 	.enable_pme_wa = rv1_enable_pme_wa,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index cfe8331c4b46..167bd6e92afa 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -1290,8 +1290,6 @@ static void dcn10_init_hw(struct dc *dc)
+ 	}
+ 
+ 	dc->hwss.enable_power_gating_plane(dc->hwseq, true);
+-
+-	memset(&dc->clk_mgr->clks, 0, sizeof(dc->clk_mgr->clks));
+ }
+ 
+ static void dcn10_reset_hw_ctx_wrap(
+-- 
+2.17.1
+