diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3397-drm-amd-display-reset-drr-programming-on-pipe-reset.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3397-drm-amd-display-reset-drr-programming-on-pipe-reset.patch | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3397-drm-amd-display-reset-drr-programming-on-pipe-reset.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3397-drm-amd-display-reset-drr-programming-on-pipe-reset.patch new file mode 100644 index 00000000..08c471df --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3397-drm-amd-display-reset-drr-programming-on-pipe-reset.patch @@ -0,0 +1,52 @@ +From 23f4b699fefc836643463331c83f1e7bcacd7b1e Mon Sep 17 00:00:00 2001 +From: Wenjing Liu <Wenjing.Liu@amd.com> +Date: Wed, 10 Jul 2019 18:31:38 -0400 +Subject: [PATCH 3397/4256] drm/amd/display: reset drr programming on pipe + reset + +[why] +drr is still enabled after driver is unloaded causing black screen + +[how] +disable drr during pipe reset. + +Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com> +Reviewed-by: Jun Lei <Jun.Lei@amd.com> +Acked-by: Leo Li <sunpeng.li@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 +++ + drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 4 ++++ + 2 files changed, 7 insertions(+) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +index 29e548ab73c4..84980d4f324d 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +@@ -822,6 +822,9 @@ static void dcn10_reset_back_end_for_pipe( + pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); + + pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); ++ if (pipe_ctx->stream_res.tg->funcs->set_drr) ++ pipe_ctx->stream_res.tg->funcs->set_drr( ++ pipe_ctx->stream_res.tg, NULL); + } + + for (i = 0; i < dc->res_pool->pipe_count; i++) +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +index 38b3c89b2a59..27d143418cc7 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +@@ -1834,6 +1834,10 @@ static void dcn20_reset_back_end_for_pipe( + if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) + pipe_ctx->stream_res.tg->funcs->set_odm_bypass( + pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); ++ ++ if (pipe_ctx->stream_res.tg->funcs->set_drr) ++ pipe_ctx->stream_res.tg->funcs->set_drr( ++ pipe_ctx->stream_res.tg, NULL); + } + + for (i = 0; i < dc->res_pool->pipe_count; i++) +-- +2.17.1 + |