diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3385-drm-amdgpu-add-sdma-golden-settings-for-renoir.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3385-drm-amdgpu-add-sdma-golden-settings-for-renoir.patch | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3385-drm-amdgpu-add-sdma-golden-settings-for-renoir.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3385-drm-amdgpu-add-sdma-golden-settings-for-renoir.patch new file mode 100644 index 00000000..b02c3dac --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3385-drm-amdgpu-add-sdma-golden-settings-for-renoir.patch @@ -0,0 +1,52 @@ +From e2aba1159059e62730fb7141ae859fc9a2d31bba Mon Sep 17 00:00:00 2001 +From: Huang Rui <ray.huang@amd.com> +Date: Wed, 24 Jul 2019 14:03:25 -0500 +Subject: [PATCH 3385/4256] drm/amdgpu: add sdma golden settings for renoir + +This patch adds sdma golden settings for renoir asic. + +Acked-by: Huang Rui <ray.huang@amd.com> +Signed-off-by: Huang Rui <ray.huang@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +index 0c137b476572..e336dae8be33 100644 +--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +@@ -241,6 +241,18 @@ static const struct soc15_reg_golden golden_settings_sdma_arct[] = + SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002) + }; + ++static const struct soc15_reg_golden golden_settings_sdma_4_3[] = { ++ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), ++ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), ++ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003002), ++ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003002), ++ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), ++ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003fff07, 0x40000051), ++ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), ++ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), ++ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), ++}; ++ + static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev, + u32 instance, u32 offset) + { +@@ -365,6 +377,11 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) + golden_settings_sdma_rv1, + ARRAY_SIZE(golden_settings_sdma_rv1)); + break; ++ case CHIP_RENOIR: ++ soc15_program_register_sequence(adev, ++ golden_settings_sdma_4_3, ++ ARRAY_SIZE(golden_settings_sdma_4_3)); ++ break; + default: + break; + } +-- +2.17.1 + |