aboutsummaryrefslogtreecommitdiffstats
path: root/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3384-drm-amdgpu-add-gfx-golden-settings-for-renoir-v2.patch
diff options
context:
space:
mode:
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3384-drm-amdgpu-add-gfx-golden-settings-for-renoir-v2.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3384-drm-amdgpu-add-gfx-golden-settings-for-renoir-v2.patch78
1 files changed, 78 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3384-drm-amdgpu-add-gfx-golden-settings-for-renoir-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3384-drm-amdgpu-add-gfx-golden-settings-for-renoir-v2.patch
new file mode 100644
index 00000000..3f19e443
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3384-drm-amdgpu-add-gfx-golden-settings-for-renoir-v2.patch
@@ -0,0 +1,78 @@
+From dd6744508a516e47bf3b293f16698cecab66c064 Mon Sep 17 00:00:00 2001
+From: Huang Rui <ray.huang@amd.com>
+Date: Sun, 23 Jun 2019 02:51:57 +0800
+Subject: [PATCH 3384/4256] drm/amdgpu: add gfx golden settings for renoir (v2)
+
+This patch adds gfx golden settings for renoir real asic.
+
+v2: update settings (Alex)
+
+Acked-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 26 ++++++++++++++++++++++++++
+ 1 file changed, 26 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 1df9866d8f24..75ea77cc457f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -32,6 +32,7 @@
+
+ #include "gc/gc_9_0_offset.h"
+ #include "gc/gc_9_0_sh_mask.h"
++
+ #include "vega10_enum.h"
+ #include "hdp/hdp_4_0_offset.h"
+
+@@ -56,6 +57,9 @@
+ #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x00000001L
+ #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 0x00000006L
+
++#define mmGCEA_PROBE_MAP 0x070c
++#define mmGCEA_PROBE_MAP_BASE_IDX 0
++
+ MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
+ MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
+ MODULE_FIRMWARE("amdgpu/vega10_me.bin");
+@@ -614,6 +618,23 @@ static const struct soc15_reg_golden golden_settings_gc_9_1_rv2[] =
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x3f8fffff, 0x08000080),
+ };
+
++static const struct soc15_reg_golden golden_settings_gc_9_1_rn[] =
++{
++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x3f8fffff, 0x08000080),
++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000),
++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400),
++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x22010042),
++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x22010042),
++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000),
++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120),
++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_PROBE_MAP, 0xffffffff, 0x0000cccc),
++};
++
+ static const struct soc15_reg_golden golden_settings_gc_9_x_common[] =
+ {
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0xffffffff, 0x000001ff),
+@@ -758,6 +779,11 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
+ golden_settings_gc_9_1_rv1,
+ ARRAY_SIZE(golden_settings_gc_9_1_rv1));
+ break;
++ case CHIP_RENOIR:
++ soc15_program_register_sequence(adev,
++ golden_settings_gc_9_1_rn,
++ ARRAY_SIZE(golden_settings_gc_9_1_rn));
++ break;
+ default:
+ break;
+ }
+--
+2.17.1
+