diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3355-Revert-drm-amdgpu-fix-transform-feedback-GDS-hang-on.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3355-Revert-drm-amdgpu-fix-transform-feedback-GDS-hang-on.patch | 76 |
1 files changed, 76 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3355-Revert-drm-amdgpu-fix-transform-feedback-GDS-hang-on.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3355-Revert-drm-amdgpu-fix-transform-feedback-GDS-hang-on.patch new file mode 100644 index 00000000..ebfbf381 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3355-Revert-drm-amdgpu-fix-transform-feedback-GDS-hang-on.patch @@ -0,0 +1,76 @@ +From 6ac842561a16cad68c85bff512c4646659d3ecd5 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com> +Date: Fri, 2 Aug 2019 17:44:06 -0400 +Subject: [PATCH 3355/4256] Revert "drm/amdgpu: fix transform feedback GDS hang + on gfx10 (v2)" +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This reverts commit b41335c6c0303d100abe89c843e52645d1974cd9. + +SET_CONFIG_REG writes to memory if register shadowing is enabled, +causing a VM fault. + +NGG streamout is unstable anyway, so all UMDs should use legacy +streamout. I think Mesa is the only driver using NGG streamout. + +Signed-off-by: Marek Olšák <marek.olsak@amd.com> +Reviewed-by: Le Ma <Le.Ma@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h | 1 - + drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 12 +----------- + 2 files changed, 1 insertion(+), 12 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h +index df8a23554831..f6ac1e9548f2 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h +@@ -32,7 +32,6 @@ struct amdgpu_gds { + uint32_t gws_size; + uint32_t oa_size; + uint32_t gds_compute_max_wave_id; +- uint32_t vgt_gs_max_wave_id; + }; + + struct amdgpu_gds_reg_offset { +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +index 7d3e6a3161dd..066ba593af23 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +@@ -4360,15 +4360,6 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, + unsigned vmid = AMDGPU_JOB_GET_VMID(job); + u32 header, control = 0; + +- /* Prevent a hw deadlock due to a wave ID mismatch between ME and GDS. +- * This resets the wave ID counters. (needed by transform feedback) +- * TODO: This might only be needed on a VMID switch when we change +- * the GDS OA mapping, not sure. +- */ +- amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); +- amdgpu_ring_write(ring, mmVGT_GS_MAX_WAVE_ID); +- amdgpu_ring_write(ring, ring->adev->gds.vgt_gs_max_wave_id); +- + if (ib->flags & AMDGPU_IB_FLAG_CE) + header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2); + else +@@ -5119,7 +5110,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { + 5 + /* HDP_INVL */ + 8 + 8 + /* FENCE x2 */ + 2, /* SWITCH_BUFFER */ +- .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_gfx */ ++ .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */ + .emit_ib = gfx_v10_0_ring_emit_ib_gfx, + .emit_fence = gfx_v10_0_ring_emit_fence, + .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, +@@ -5272,7 +5263,6 @@ static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev) + default: + adev->gds.gds_size = 0x10000; + adev->gds.gds_compute_max_wave_id = 0x4ff; +- adev->gds.vgt_gs_max_wave_id = 0x3ff; + break; + } + +-- +2.17.1 + |