diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3354-drm-amdgpu-handle-AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_.patch')
-rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3354-drm-amdgpu-handle-AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_.patch | 71 |
1 files changed, 71 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3354-drm-amdgpu-handle-AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3354-drm-amdgpu-handle-AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_.patch new file mode 100644 index 00000000..cd43d868 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3354-drm-amdgpu-handle-AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_.patch @@ -0,0 +1,71 @@ +From 5c2be5f5d4d600e258d4d6465ed621952ab67c1f Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com> +Date: Wed, 19 Jun 2019 19:26:59 -0400 +Subject: [PATCH 3354/4256] drm/amdgpu: handle + AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID on gfx10 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Marek Olšák <marek.olsak@amd.com> +Acked-by: Christian König <christian.koenig@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 21 +++++++++++++++++++-- + 1 file changed, 19 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +index ba8f66f27d2f..7d3e6a3161dd 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +@@ -4406,6 +4406,22 @@ static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring, + unsigned vmid = AMDGPU_JOB_GET_VMID(job); + u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); + ++ /* Currently, there is a high possibility to get wave ID mismatch ++ * between ME and GDS, leading to a hw deadlock, because ME generates ++ * different wave IDs than the GDS expects. This situation happens ++ * randomly when at least 5 compute pipes use GDS ordered append. ++ * The wave IDs generated by ME are also wrong after suspend/resume. ++ * Those are probably bugs somewhere else in the kernel driver. ++ * ++ * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and ++ * GDS to 0 for this ring (me/pipe). ++ */ ++ if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { ++ amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); ++ amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); ++ amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); ++ } ++ + amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); + BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ + amdgpu_ring_write(ring, +@@ -5142,7 +5158,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + + 2 + /* gfx_v10_0_ring_emit_vm_flush */ + 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */ +- .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_compute */ ++ .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ + .emit_ib = gfx_v10_0_ring_emit_ib_compute, + .emit_fence = gfx_v10_0_ring_emit_fence, + .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, +@@ -5175,7 +5191,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = { + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + + 2 + /* gfx_v10_0_ring_emit_vm_flush */ + 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */ +- .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_compute */ ++ .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ + .emit_ib = gfx_v10_0_ring_emit_ib_compute, + .emit_fence = gfx_v10_0_ring_emit_fence_kiq, + .test_ring = gfx_v10_0_ring_test_ring, +@@ -5255,6 +5271,7 @@ static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev) + case CHIP_NAVI10: + default: + adev->gds.gds_size = 0x10000; ++ adev->gds.gds_compute_max_wave_id = 0x4ff; + adev->gds.vgt_gs_max_wave_id = 0x3ff; + break; + } +-- +2.17.1 + |