diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3345-drm-amdgpu-Update-pitch-on-page-flips-without-DC-as-.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3345-drm-amdgpu-Update-pitch-on-page-flips-without-DC-as-.patch | 124 |
1 files changed, 124 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3345-drm-amdgpu-Update-pitch-on-page-flips-without-DC-as-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3345-drm-amdgpu-Update-pitch-on-page-flips-without-DC-as-.patch new file mode 100644 index 00000000..53e08208 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3345-drm-amdgpu-Update-pitch-on-page-flips-without-DC-as-.patch @@ -0,0 +1,124 @@ +From b864d1ec92247f632c524dd7babe1cd3aeb4b159 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Michel=20D=C3=A4nzer?= <michel.daenzer@amd.com> +Date: Wed, 24 Jul 2019 17:56:28 +0200 +Subject: [PATCH 3345/4256] drm/amdgpu: Update pitch on page flips without DC + as well +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +DC already handles this correctly since amdgpu minor version 31. Bump +the minor version again so that xf86-video-amdgpu can take advantage of +this working without DC as well now. + +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++- + drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 4 ++++ + drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 4 ++++ + drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 4 ++++ + drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 4 ++++ + 5 files changed, 18 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +index 2c0e077d209f..7d3a39cebd90 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +@@ -77,9 +77,10 @@ + * - 3.31.0 - Add support for per-flip tiling attribute changes with DC + * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. + * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. ++ * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches + */ + #define KMS_DRIVER_MAJOR 3 +-#define KMS_DRIVER_MINOR 33 ++#define KMS_DRIVER_MINOR 34 + #define KMS_DRIVER_PATCHLEVEL 0 + + #define AMDGPU_VERSION "19.10.9.418" +diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +index 4cfecdce29a3..6cc3498fce9e 100644 +--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +@@ -233,6 +233,7 @@ static void dce_v10_0_page_flip(struct amdgpu_device *adev, + int crtc_id, u64 crtc_base, bool async) + { + struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; ++ struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb; + u32 tmp; + + /* flip at hsync for async, default is vsync */ +@@ -240,6 +241,9 @@ static void dce_v10_0_page_flip(struct amdgpu_device *adev, + tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, + GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0); + WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); ++ /* update pitch */ ++ WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, ++ fb->pitches[0] / fb->format->cpp[0]); + /* update the primary scanout address */ + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, + upper_32_bits(crtc_base)); +diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +index 7c868916d90f..73b91e1f1cd9 100644 +--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +@@ -251,6 +251,7 @@ static void dce_v11_0_page_flip(struct amdgpu_device *adev, + int crtc_id, u64 crtc_base, bool async) + { + struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; ++ struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb; + u32 tmp; + + /* flip immediate for async, default is vsync */ +@@ -258,6 +259,9 @@ static void dce_v11_0_page_flip(struct amdgpu_device *adev, + tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, + GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0); + WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); ++ /* update pitch */ ++ WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, ++ fb->pitches[0] / fb->format->cpp[0]); + /* update the scanout addresses */ + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, + upper_32_bits(crtc_base)); +diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +index 3a707b8618b7..04c81df035c3 100644 +--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +@@ -186,10 +186,14 @@ static void dce_v6_0_page_flip(struct amdgpu_device *adev, + int crtc_id, u64 crtc_base, bool async) + { + struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; ++ struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb; + + /* flip at hsync for async, default is vsync */ + WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? + GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0); ++ /* update pitch */ ++ WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, ++ fb->pitches[0] / fb->format->cpp[0]); + /* update the scanout addresses */ + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, + upper_32_bits(crtc_base)); +diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +index 8c0576978d36..b239b04bd6c0 100644 +--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +@@ -181,10 +181,14 @@ static void dce_v8_0_page_flip(struct amdgpu_device *adev, + int crtc_id, u64 crtc_base, bool async) + { + struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; ++ struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb; + + /* flip at hsync for async, default is vsync */ + WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? + GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0); ++ /* update pitch */ ++ WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, ++ fb->pitches[0] / fb->format->cpp[0]); + /* update the primary scanout addresses */ + WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, + upper_32_bits(crtc_base)); +-- +2.17.1 + |