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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3324-drm-amdgpu-support-sdma-clock-gating-for-more-instan.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3324-drm-amdgpu-support-sdma-clock-gating-for-more-instan.patch154
1 files changed, 154 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3324-drm-amdgpu-support-sdma-clock-gating-for-more-instan.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3324-drm-amdgpu-support-sdma-clock-gating-for-more-instan.patch
new file mode 100644
index 00000000..83001590
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3324-drm-amdgpu-support-sdma-clock-gating-for-more-instan.patch
@@ -0,0 +1,154 @@
+From 8dc0c3a6785b524ec831b1414674e8110cee966f Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Wed, 7 Aug 2019 15:45:25 +0800
+Subject: [PATCH 3324/4256] drm/amdgpu: support sdma clock gating for more
+ instances
+
+Shorten the code with RREG32_SDMA/WREG32_SDMA macro in CG part.
+
+Change-Id: Icbf94169bb703877b105a307f14c708609faaae4
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 105 ++++++++-----------------
+ 1 file changed, 34 insertions(+), 71 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index af80f3782811..84ad12c1e601 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -2085,61 +2085,35 @@ static void sdma_v4_0_update_medium_grain_clock_gating(
+ bool enable)
+ {
+ uint32_t data, def;
++ int i;
+
+ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
+- /* enable sdma0 clock gating */
+- def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
+- data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
+- SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
+- SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
+- SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
+- SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
+- SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
+- SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
+- SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
+- if (def != data)
+- WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data);
+-
+- if (adev->sdma.num_instances > 1) {
+- def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL));
+- data &= ~(SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK |
+- SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK |
+- SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK |
+- SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK |
+- SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK |
+- SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK |
+- SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK |
+- SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK);
++ for (i = 0; i < adev->sdma.num_instances; i++) {
++ def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL);
++ data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
++ SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
++ SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
++ SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
++ SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
++ SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
++ SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
++ SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
+ if (def != data)
+- WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data);
++ WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data);
+ }
+ } else {
+- /* disable sdma0 clock gating */
+- def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
+- data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
+- SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
+- SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
+- SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
+- SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
+- SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
+- SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
+- SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
+-
+- if (def != data)
+- WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data);
+-
+- if (adev->sdma.num_instances > 1) {
+- def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL));
+- data |= (SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK |
+- SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK |
+- SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK |
+- SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK |
+- SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK |
+- SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK |
+- SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK |
+- SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK);
++ for (i = 0; i < adev->sdma.num_instances; i++) {
++ def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL);
++ data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
++ SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
++ SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
++ SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
++ SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
++ SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
++ SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
++ SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
+ if (def != data)
+- WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data);
++ WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data);
+ }
+ }
+ }
+@@ -2150,34 +2124,23 @@ static void sdma_v4_0_update_medium_grain_light_sleep(
+ bool enable)
+ {
+ uint32_t data, def;
++ int i;
+
+ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
+- /* 1-not override: enable sdma0 mem light sleep */
+- def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
+- data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
+- if (def != data)
+- WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
+-
+- /* 1-not override: enable sdma1 mem light sleep */
+- if (adev->sdma.num_instances > 1) {
+- def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL));
+- data |= SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
++ for (i = 0; i < adev->sdma.num_instances; i++) {
++ /* 1-not override: enable sdma mem light sleep */
++ def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL);
++ data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
+ if (def != data)
+- WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data);
++ WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data);
+ }
+ } else {
+- /* 0-override:disable sdma0 mem light sleep */
+- def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
+- data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
+- if (def != data)
+- WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
+-
+- /* 0-override:disable sdma1 mem light sleep */
+- if (adev->sdma.num_instances > 1) {
+- def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL));
+- data &= ~SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
++ for (i = 0; i < adev->sdma.num_instances; i++) {
++ /* 0-override:disable sdma mem light sleep */
++ def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL);
++ data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
+ if (def != data)
+- WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data);
++ WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data);
+ }
+ }
+ }
+--
+2.17.1
+