diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3284-drm-amdgpu-gfx10-set-tcp-harvest-for-navi12.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3284-drm-amdgpu-gfx10-set-tcp-harvest-for-navi12.patch | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3284-drm-amdgpu-gfx10-set-tcp-harvest-for-navi12.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3284-drm-amdgpu-gfx10-set-tcp-harvest-for-navi12.patch new file mode 100644 index 00000000..bdc4f0e8 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3284-drm-amdgpu-gfx10-set-tcp-harvest-for-navi12.patch @@ -0,0 +1,50 @@ +From 7533ce2befc6ca4bab1a0ab7abbeb56b759d9b2c Mon Sep 17 00:00:00 2001 +From: Xiaojie Yuan <xiaojie.yuan@amd.com> +Date: Tue, 29 Jan 2019 22:36:15 +0800 +Subject: [PATCH 3284/4256] drm/amdgpu/gfx10: set tcp harvest for navi12 + +Same as navi10. + +Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> +Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 8 +++++--- + 1 file changed, 5 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +index 716b812c9d31..eeb381029b07 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +@@ -1563,7 +1563,7 @@ static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) + u32 utcl_invreq_disable = 0; + /* + * GCRD_TARGETS_DISABLE field contains +- * for Navi10: GL1C=[18:15], SQC=[14:10], TCP=[9:0] ++ * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0] + * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0] + */ + u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask( +@@ -1572,7 +1572,7 @@ static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) + 4); /* GL1C */ + /* + * UTCL1_UTCL0_INVREQ_DISABLE field contains +- * for Navi10: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0] ++ * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0] + * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0] + */ + u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask( +@@ -1581,7 +1581,9 @@ static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) + 4 + /* RMI */ + 1); /* SQG */ + +- if (adev->asic_type == CHIP_NAVI10 || adev->asic_type == CHIP_NAVI14) { ++ if (adev->asic_type == CHIP_NAVI10 || ++ adev->asic_type == CHIP_NAVI14 || ++ adev->asic_type == CHIP_NAVI12) { + mutex_lock(&adev->grbm_idx_mutex); + for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { + for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { +-- +2.17.1 + |