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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3282-drm-amdgpu-gmc10-set-gart-size-and-vm-size-for-navi1.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3282-drm-amdgpu-gmc10-set-gart-size-and-vm-size-for-navi1.patch51
1 files changed, 51 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3282-drm-amdgpu-gmc10-set-gart-size-and-vm-size-for-navi1.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3282-drm-amdgpu-gmc10-set-gart-size-and-vm-size-for-navi1.patch
new file mode 100644
index 00000000..e2840e10
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3282-drm-amdgpu-gmc10-set-gart-size-and-vm-size-for-navi1.patch
@@ -0,0 +1,51 @@
+From a456a8b243d0248f16035fa8d603076ae0a08b4a Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Thu, 16 May 2019 18:05:37 +0800
+Subject: [PATCH 3282/4256] drm/amdgpu/gmc10: set gart size and vm size for
+ navi12
+
+Same as other navi asics.
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+index a0bd14e9b8fe..4e3ac1084a94 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+@@ -525,6 +525,7 @@ static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
+ switch (adev->asic_type) {
+ case CHIP_NAVI10:
+ case CHIP_NAVI14:
++ case CHIP_NAVI12:
+ default:
+ adev->gmc.gart_size = 512ULL << 20;
+ break;
+@@ -603,10 +604,11 @@ static int gmc_v10_0_sw_init(void *handle)
+ switch (adev->asic_type) {
+ case CHIP_NAVI10:
+ case CHIP_NAVI14:
++ case CHIP_NAVI12:
+ adev->num_vmhubs = 2;
+ /*
+ * To fulfill 4-level page support,
+- * vm size is 256TB (48bit), maximum size of Navi10/Navi14,
++ * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12,
+ * block size 512 (9bit)
+ */
+ amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
+@@ -721,6 +723,7 @@ static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev)
+ switch (adev->asic_type) {
+ case CHIP_NAVI10:
+ case CHIP_NAVI14:
++ case CHIP_NAVI12:
+ break;
+ default:
+ break;
+--
+2.17.1
+