diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3277-drm-amdgpu-gfx10-add-placeholder-for-navi12-golden-s.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3277-drm-amdgpu-gfx10-add-placeholder-for-navi12-golden-s.patch | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3277-drm-amdgpu-gfx10-add-placeholder-for-navi12-golden-s.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3277-drm-amdgpu-gfx10-add-placeholder-for-navi12-golden-s.patch new file mode 100644 index 00000000..24e3a495 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3277-drm-amdgpu-gfx10-add-placeholder-for-navi12-golden-s.patch @@ -0,0 +1,49 @@ +From 54b0293967a4f41d2f84d6d75d281c79bb5f507c Mon Sep 17 00:00:00 2001 +From: Xiaojie Yuan <xiaojie.yuan@amd.com> +Date: Tue, 11 Jun 2019 11:16:54 +0800 +Subject: [PATCH 3277/4256] drm/amdgpu/gfx10: add placeholder for navi12 golden + settings + +Not used yet. + +Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> +Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +index cf7afdad267d..ecbe3349bcfd 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +@@ -170,6 +170,11 @@ static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = + /* Pending on emulation bring up */ + }; + ++static const struct soc15_reg_golden golden_settings_gc_10_1_nv12[] = ++{ ++ /* Pending on emulation bring up */ ++}; ++ + #define DEFAULT_SH_MEM_CONFIG \ + ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ + (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ +@@ -319,6 +324,14 @@ static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) + golden_settings_gc_10_1_nv14, + (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14)); + break; ++ case CHIP_NAVI12: ++ soc15_program_register_sequence(adev, ++ golden_settings_gc_10_1, ++ (const u32)ARRAY_SIZE(golden_settings_gc_10_1)); ++ soc15_program_register_sequence(adev, ++ golden_settings_gc_10_1_nv12, ++ (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv12)); ++ break; + default: + break; + } +-- +2.17.1 + |