diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3275-drm-amdgpu-gfx10-add-gfx-config-for-navi12.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3275-drm-amdgpu-gfx10-add-gfx-config-for-navi12.patch | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3275-drm-amdgpu-gfx10-add-gfx-config-for-navi12.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3275-drm-amdgpu-gfx10-add-gfx-config-for-navi12.patch new file mode 100644 index 00000000..afa39568 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3275-drm-amdgpu-gfx10-add-gfx-config-for-navi12.patch @@ -0,0 +1,45 @@ +From f515f542e67ca39fb62b223eb3215eb466b15cfd Mon Sep 17 00:00:00 2001 +From: Xiaojie Yuan <xiaojie.yuan@amd.com> +Date: Thu, 16 May 2019 19:01:19 +0800 +Subject: [PATCH 3275/4256] drm/amdgpu/gfx10: add gfx config for navi12 + +got from mmCP_MAX_CONTEXT and mmPA_SC_FIFO_SIZE + +v2: squash all navi asics together because the +settings are the same. + +Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> +Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 10 ++-------- + 1 file changed, 2 insertions(+), 8 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +index 313009f11207..0c7395a37c68 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +@@ -1091,18 +1091,12 @@ static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) + + switch (adev->asic_type) { + case CHIP_NAVI10: +- adev->gfx.config.max_hw_contexts = 8; +- adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; +- adev->gfx.config.sc_prim_fifo_size_backend = 0x100; +- adev->gfx.config.sc_hiz_tile_fifo_size = 0; +- adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; +- gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); +- break; + case CHIP_NAVI14: ++ case CHIP_NAVI12: + adev->gfx.config.max_hw_contexts = 8; + adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; + adev->gfx.config.sc_prim_fifo_size_backend = 0x100; +- adev->gfx.config.sc_hiz_tile_fifo_size = 0x0; ++ adev->gfx.config.sc_hiz_tile_fifo_size = 0; + adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; + gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); + break; +-- +2.17.1 + |