diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3267-drm-amdgpu-initialize-reg-base-for-navi12.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3267-drm-amdgpu-initialize-reg-base-for-navi12.patch | 131 |
1 files changed, 131 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3267-drm-amdgpu-initialize-reg-base-for-navi12.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3267-drm-amdgpu-initialize-reg-base-for-navi12.patch new file mode 100644 index 00000000..456afd25 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3267-drm-amdgpu-initialize-reg-base-for-navi12.patch @@ -0,0 +1,131 @@ +From da527aa4ee827be7c1497ff4b45103dcdb040930 Mon Sep 17 00:00:00 2001 +From: Xiaojie Yuan <xiaojie.yuan@amd.com> +Date: Tue, 14 May 2019 15:22:53 +0800 +Subject: [PATCH 3267/4256] drm/amdgpu: initialize reg base for navi12 + +Set up the register offset map for navi12. + +Change-Id: I4b48592e8474db17634b10183c98cd399f0203aa +Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> +Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- + drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c | 53 ++++++++++++++++++++ + drivers/gpu/drm/amd/amdgpu/nv.c | 3 ++ + drivers/gpu/drm/amd/amdgpu/nv.h | 1 + + include/drm/amd_asic_type.h | 1 + + 5 files changed, 59 insertions(+), 1 deletion(-) + create mode 100644 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c + +diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile +index 797f8a7e4f72..651d77c59ba3 100644 +--- a/drivers/gpu/drm/amd/amdgpu/Makefile ++++ b/drivers/gpu/drm/amd/amdgpu/Makefile +@@ -67,7 +67,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce + amdgpu-y += \ + vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \ + vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o navi14_reg_init.o \ +- arct_reg_init.o ++ arct_reg_init.o navi12_reg_init.o + + # add DF block + amdgpu-y += \ +diff --git a/drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c b/drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c +new file mode 100644 +index 000000000000..cadc7603ca41 +--- /dev/null ++++ b/drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c +@@ -0,0 +1,53 @@ ++/* ++ * Copyright 2018 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ */ ++#include "amdgpu.h" ++#include "nv.h" ++ ++#include "soc15_common.h" ++#include "soc15_hw_ip.h" ++#include "navi12_ip_offset.h" ++ ++int navi12_reg_base_init(struct amdgpu_device *adev) ++{ ++ /* HW has more IP blocks, only initialized the blocks needed by driver */ ++ uint32_t i; ++ for (i = 0 ; i < MAX_INSTANCE ; ++i) { ++ adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); ++ adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); ++ adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); ++ adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); ++ adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i])); ++ adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); ++ adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); ++ adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(UVD0_BASE.instance[i])); ++ adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); ++ adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DMU_BASE.instance[i])); ++ adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); ++ adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); ++ adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); ++ adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i])); ++ adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); ++ adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i])); ++ } ++ return 0; ++} +diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c +index bf4cbcdeef78..1e0852c28c93 100644 +--- a/drivers/gpu/drm/amd/amdgpu/nv.c ++++ b/drivers/gpu/drm/amd/amdgpu/nv.c +@@ -385,6 +385,9 @@ int nv_set_ip_blocks(struct amdgpu_device *adev) + case CHIP_NAVI14: + navi14_reg_base_init(adev); + break; ++ case CHIP_NAVI12: ++ navi12_reg_base_init(adev); ++ break; + default: + return -EINVAL; + } +diff --git a/drivers/gpu/drm/amd/amdgpu/nv.h b/drivers/gpu/drm/amd/amdgpu/nv.h +index 332d5cdc308e..82e6cb432f3d 100644 +--- a/drivers/gpu/drm/amd/amdgpu/nv.h ++++ b/drivers/gpu/drm/amd/amdgpu/nv.h +@@ -31,4 +31,5 @@ void nv_grbm_select(struct amdgpu_device *adev, + int nv_set_ip_blocks(struct amdgpu_device *adev); + int navi10_reg_base_init(struct amdgpu_device *adev); + int navi14_reg_base_init(struct amdgpu_device *adev); ++int navi12_reg_base_init(struct amdgpu_device *adev); + #endif +diff --git a/include/drm/amd_asic_type.h b/include/drm/amd_asic_type.h +index 5595483933aa..4fce10a2bbee 100644 +--- a/include/drm/amd_asic_type.h ++++ b/include/drm/amd_asic_type.h +@@ -53,6 +53,7 @@ enum amd_asic_type { + CHIP_PICASSO, + CHIP_NAVI10, + CHIP_NAVI14, ++ CHIP_NAVI12, + CHIP_LAST, + }; + +-- +2.17.1 + |