diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3253-drm-amdgpu-update-the-calc-algorithm-of-umc-ecc-erro.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3253-drm-amdgpu-update-the-calc-algorithm-of-umc-ecc-erro.patch | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3253-drm-amdgpu-update-the-calc-algorithm-of-umc-ecc-erro.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3253-drm-amdgpu-update-the-calc-algorithm-of-umc-ecc-erro.patch new file mode 100644 index 00000000..ecd50f0c --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3253-drm-amdgpu-update-the-calc-algorithm-of-umc-ecc-erro.patch @@ -0,0 +1,48 @@ +From d824d5a05162198195d9bbcaa8ae1fd8cde628e2 Mon Sep 17 00:00:00 2001 +From: Tao Zhou <tao.zhou1@amd.com> +Date: Mon, 29 Jul 2019 17:19:57 +0800 +Subject: [PATCH 3253/4256] drm/amdgpu: update the calc algorithm of umc ecc + error count + +the initial value of ecc error count can be adjusted + +Signed-off-by: Tao Zhou <tao.zhou1@amd.com> +Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/umc_v6_1.c | 10 ++++++---- + 1 file changed, 6 insertions(+), 4 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c +index 0ab2e96b4f77..64df37b860dd 100644 +--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c ++++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c +@@ -98,9 +98,10 @@ static void umc_v6_1_query_correctable_error_count(struct amdgpu_device *adev, + WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel); + ecc_err_cnt = RREG32(ecc_err_cnt_addr + umc_reg_offset); + *error_count += +- REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt); ++ (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) - ++ UMC_V6_1_CE_CNT_INIT); + /* clear the lower chip err count */ +- WREG32(ecc_err_cnt_addr + umc_reg_offset, 0); ++ WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT); + + /* select the higher chip and check the err counter */ + ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel, +@@ -108,9 +109,10 @@ static void umc_v6_1_query_correctable_error_count(struct amdgpu_device *adev, + WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel); + ecc_err_cnt = RREG32(ecc_err_cnt_addr + umc_reg_offset); + *error_count += +- REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt); ++ (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) - ++ UMC_V6_1_CE_CNT_INIT); + /* clear the higher chip err count */ +- WREG32(ecc_err_cnt_addr + umc_reg_offset, 0); ++ WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT); + + /* check for SRAM correctable error + MCUMC_STATUS is a 64 bit register */ +-- +2.17.1 + |