diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3246-drm-amdgpu-add-more-parameters-and-functions-to-amdg.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3246-drm-amdgpu-add-more-parameters-and-functions-to-amdg.patch | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3246-drm-amdgpu-add-more-parameters-and-functions-to-amdg.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3246-drm-amdgpu-add-more-parameters-and-functions-to-amdg.patch new file mode 100644 index 00000000..15647b0c --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3246-drm-amdgpu-add-more-parameters-and-functions-to-amdg.patch @@ -0,0 +1,65 @@ +From 0827eb7f189a8419a457b0bfe73c7927a8bcca10 Mon Sep 17 00:00:00 2001 +From: Tao Zhou <tao.zhou1@amd.com> +Date: Mon, 29 Jul 2019 14:10:54 +0800 +Subject: [PATCH 3246/4256] drm/amdgpu: add more parameters and functions to + amdgpu_umc structure + +expose more parameters and functions of specific umc version to common +umc layer, so amdgpu_umc layer and other blocks could access them + +Signed-off-by: Tao Zhou <tao.zhou1@amd.com> +Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h | 13 +++++++++++++ + drivers/gpu/drm/amd/amdgpu/umc_v6_1.h | 2 ++ + 2 files changed, 15 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h +index dfa1a39e57af..2604f5076867 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h +@@ -22,15 +22,28 @@ + #define __AMDGPU_UMC_H__ + + struct amdgpu_umc_funcs { ++ void (*ras_init)(struct amdgpu_device *adev); + void (*query_ras_error_count)(struct amdgpu_device *adev, + void *ras_error_status); + void (*query_ras_error_address)(struct amdgpu_device *adev, + void *ras_error_status); ++ void (*enable_umc_index_mode)(struct amdgpu_device *adev, ++ uint32_t umc_instance); ++ void (*disable_umc_index_mode)(struct amdgpu_device *adev); + }; + + struct amdgpu_umc { + /* max error count in one ras query call */ + uint32_t max_ras_err_cnt_per_query; ++ /* number of umc channel instance with memory map register access */ ++ uint32_t channel_inst_num; ++ /* number of umc instance with memory map register access */ ++ uint32_t umc_inst_num; ++ /* UMC regiser per channel offset */ ++ uint32_t channel_offs; ++ /* channel index table of interleaved memory */ ++ const uint32_t *channel_idx_tbl; ++ + const struct amdgpu_umc_funcs *funcs; + }; + +diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h +index d25ae414f4d8..bddaf14a77f9 100644 +--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h ++++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h +@@ -31,6 +31,8 @@ + #define UMC_V6_1_CHANNEL_INSTANCE_NUM 4 + /* number of umc instance with memory map register access */ + #define UMC_V6_1_UMC_INSTANCE_NUM 8 ++/* total channel instances in one umc block */ ++#define UMC_V6_1_TOTAL_CHANNEL_NUM (UMC_V6_1_CHANNEL_INSTANCE_NUM * UMC_V6_1_UMC_INSTANCE_NUM) + /* UMC regiser per channel offset */ + #define UMC_V6_1_PER_CHANNEL_OFFSET 0x800 + +-- +2.17.1 + |