diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3233-drm-amdgpu-Fix-pcie_bw-on-Vega20.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3233-drm-amdgpu-Fix-pcie_bw-on-Vega20.patch | 105 |
1 files changed, 105 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3233-drm-amdgpu-Fix-pcie_bw-on-Vega20.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3233-drm-amdgpu-Fix-pcie_bw-on-Vega20.patch new file mode 100644 index 00000000..1197864e --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3233-drm-amdgpu-Fix-pcie_bw-on-Vega20.patch @@ -0,0 +1,105 @@ +From dd7ccac5720f796a9a63dbe4833031ab8f4c3f70 Mon Sep 17 00:00:00 2001 +From: Kent Russell <kent.russell@amd.com> +Date: Wed, 31 Jul 2019 09:24:32 -0400 +Subject: [PATCH 3233/4256] drm/amdgpu: Fix pcie_bw on Vega20 + +The registers used for VG20 are different in that certain performance +counters were split off to TXCLK3/4. Vega10/12 doesn't have this, so add +a new vg20_get_pcie_usage to reflect this change. + +Change-Id: Iec4bf608411b46f0827e7ffeb74ce93e1fd3d1b8 +Signed-off-by: Kent Russell <kent.russell@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/soc15.c | 60 ++++++++++++++++++++++++++---- + 1 file changed, 52 insertions(+), 8 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c +index 543f19b6655d..125ba1b15b6a 100644 +--- a/drivers/gpu/drm/amd/amdgpu/soc15.c ++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c +@@ -784,14 +784,9 @@ static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, + + /* Set the 2 events that we wish to watch, defined above */ + /* Reg 40 is # received msgs */ ++ /* Reg 104 is # of posted requests sent */ + perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40); +- /* Pre-VG20, Reg 104 is # of posted requests sent. On VG20 it's 108 */ +- if (adev->asic_type == CHIP_VEGA20) +- perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, +- EVENT1_SEL, 108); +- else +- perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, +- EVENT1_SEL, 104); ++ perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104); + + /* Write to enable desired perf counters */ + WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr); +@@ -821,6 +816,55 @@ static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, + *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); + } + ++static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, ++ uint64_t *count1) ++{ ++ uint32_t perfctr = 0; ++ uint64_t cnt0_of, cnt1_of; ++ int tmp; ++ ++ /* This reports 0 on APUs, so return to avoid writing/reading registers ++ * that may or may not be different from their GPU counterparts ++ */ ++ if (adev->flags & AMD_IS_APU) ++ return; ++ ++ /* Set the 2 events that we wish to watch, defined above */ ++ /* Reg 40 is # received msgs */ ++ /* Reg 108 is # of posted requests sent on VG20 */ ++ perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, ++ EVENT0_SEL, 40); ++ perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, ++ EVENT1_SEL, 108); ++ ++ /* Write to enable desired perf counters */ ++ WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr); ++ /* Zero out and enable the perf counters ++ * Write 0x5: ++ * Bit 0 = Start all counters(1) ++ * Bit 2 = Global counter reset enable(1) ++ */ ++ WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); ++ ++ msleep(1000); ++ ++ /* Load the shadow and disable the perf counters ++ * Write 0x2: ++ * Bit 0 = Stop counters(0) ++ * Bit 1 = Load the shadow counters(1) ++ */ ++ WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); ++ ++ /* Read register values to get any >32bit overflow */ ++ tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3); ++ cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER); ++ cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER); ++ ++ /* Get the values and add the overflow */ ++ *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32); ++ *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32); ++} ++ + static bool soc15_need_reset_on_init(struct amdgpu_device *adev) + { + u32 sol_reg; +@@ -892,7 +936,7 @@ static const struct amdgpu_asic_funcs vega20_asic_funcs = + .invalidate_hdp = &soc15_invalidate_hdp, + .need_full_reset = &soc15_need_full_reset, + .init_doorbell_index = &vega20_doorbell_index_init, +- .get_pcie_usage = &soc15_get_pcie_usage, ++ .get_pcie_usage = &vega20_get_pcie_usage, + .need_reset_on_init = &soc15_need_reset_on_init, + .get_pcie_replay_count = &soc15_get_pcie_replay_count, + .reset_method = &soc15_asic_reset_method +-- +2.17.1 + |