diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3232-drm-amdgpu-Update-NBIO-headers-to-add-TXCLK3-4.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3232-drm-amdgpu-Update-NBIO-headers-to-add-TXCLK3-4.patch | 76 |
1 files changed, 76 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3232-drm-amdgpu-Update-NBIO-headers-to-add-TXCLK3-4.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3232-drm-amdgpu-Update-NBIO-headers-to-add-TXCLK3-4.patch new file mode 100644 index 00000000..bf2cd004 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3232-drm-amdgpu-Update-NBIO-headers-to-add-TXCLK3-4.patch @@ -0,0 +1,76 @@ +From 54427ac8bb6fbe9a4d311960311669f9f94e6974 Mon Sep 17 00:00:00 2001 +From: Kent Russell <kent.russell@amd.com> +Date: Wed, 31 Jul 2019 09:23:45 -0400 +Subject: [PATCH 3232/4256] drm/amdgpu: Update NBIO headers to add TXCLK3/4 + +These are added for VG20, and are needed for PCIe bandwidth. + +Change-Id: I54474bb53ed563d083521d24944f5f97d372f001 +Signed-off-by: Kent Russell <kent.russell@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +--- + .../include/asic_reg/nbio/nbio_7_0_sh_mask.h | 30 +++++++++++++++++++ + .../amd/include/asic_reg/nbio/nbio_7_0_smn.h | 6 ++++ + 2 files changed, 36 insertions(+) + +diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h +index 88602479a1aa..ee8c15e4543d 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h +@@ -74709,6 +74709,36 @@ + //PCIE_PERF_COUNT1_TXCLK2 + #define PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT 0x0 + #define PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK 0xFFFFFFFFL ++//PCIE_PERF_CNTL_TXCLK3 ++#define PCIE_PERF_CNTL_TXCLK3__EVENT0_SEL__SHIFT 0x0 ++#define PCIE_PERF_CNTL_TXCLK3__EVENT1_SEL__SHIFT 0x8 ++#define PCIE_PERF_CNTL_TXCLK3__COUNTER0_UPPER__SHIFT 0x10 ++#define PCIE_PERF_CNTL_TXCLK3__COUNTER1_UPPER__SHIFT 0x18 ++#define PCIE_PERF_CNTL_TXCLK3__EVENT0_SEL_MASK 0x000000FFL ++#define PCIE_PERF_CNTL_TXCLK3__EVENT1_SEL_MASK 0x0000FF00L ++#define PCIE_PERF_CNTL_TXCLK3__COUNTER0_UPPER_MASK 0x00FF0000L ++#define PCIE_PERF_CNTL_TXCLK3__COUNTER1_UPPER_MASK 0xFF000000L ++//PCIE_PERF_COUNT0_TXCLK3 ++#define PCIE_PERF_COUNT0_TXCLK3__COUNTER0__SHIFT 0x0 ++#define PCIE_PERF_COUNT0_TXCLK3__COUNTER0_MASK 0xFFFFFFFFL ++//PCIE_PERF_COUNT1_TXCLK3 ++#define PCIE_PERF_COUNT1_TXCLK3__COUNTER1__SHIFT 0x0 ++#define PCIE_PERF_COUNT1_TXCLK3__COUNTER1_MASK 0xFFFFFFFFL ++//PCIE_PERF_CNTL_TXCLK4 ++#define PCIE_PERF_CNTL_TXCLK4__EVENT0_SEL__SHIFT 0x0 ++#define PCIE_PERF_CNTL_TXCLK4__EVENT1_SEL__SHIFT 0x8 ++#define PCIE_PERF_CNTL_TXCLK4__COUNTER0_UPPER__SHIFT 0x10 ++#define PCIE_PERF_CNTL_TXCLK4__COUNTER1_UPPER__SHIFT 0x18 ++#define PCIE_PERF_CNTL_TXCLK4__EVENT0_SEL_MASK 0x000000FFL ++#define PCIE_PERF_CNTL_TXCLK4__EVENT1_SEL_MASK 0x0000FF00L ++#define PCIE_PERF_CNTL_TXCLK4__COUNTER0_UPPER_MASK 0x00FF0000L ++#define PCIE_PERF_CNTL_TXCLK4__COUNTER1_UPPER_MASK 0xFF000000L ++//PCIE_PERF_COUNT0_TXCLK4 ++#define PCIE_PERF_COUNT0_TXCLK4__COUNTER0__SHIFT 0x0 ++#define PCIE_PERF_COUNT0_TXCLK4__COUNTER0_MASK 0xFFFFFFFFL ++//PCIE_PERF_COUNT1_TXCLK4 ++#define PCIE_PERF_COUNT1_TXCLK4__COUNTER1__SHIFT 0x0 ++#define PCIE_PERF_COUNT1_TXCLK4__COUNTER1_MASK 0xFFFFFFFFL + //PCIE_PRBS_CLR + #define PCIE_PRBS_CLR__PRBS_CLR__SHIFT 0x0 + #define PCIE_PRBS_CLR__PRBS_POLARITY_EN__SHIFT 0x18 +diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h +index caf5ffdc130a..6702575bc6e3 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h +@@ -50,6 +50,12 @@ + #define smnPCIE_PERF_CNTL_TXCLK2 0x11180254 + #define smnPCIE_PERF_COUNT0_TXCLK2 0x11180258 + #define smnPCIE_PERF_COUNT1_TXCLK2 0x1118025c ++#define smnPCIE_PERF_CNTL_TXCLK3 0x1118021c ++#define smnPCIE_PERF_COUNT0_TXCLK3 0x11180220 ++#define smnPCIE_PERF_COUNT1_TXCLK3 0x11180224 ++#define smnPCIE_PERF_CNTL_TXCLK4 0x11180228 ++#define smnPCIE_PERF_COUNT0_TXCLK4 0x1118022c ++#define smnPCIE_PERF_COUNT1_TXCLK4 0x11180230 + + #define smnPCIE_RX_NUM_NAK 0x11180038 + #define smnPCIE_RX_NUM_NAK_GENERATED 0x1118003c +-- +2.17.1 + |