aboutsummaryrefslogtreecommitdiffstats
path: root/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3225-drm-amdgpu-fix-double-ucode-load-by-PSP-v3.patch
diff options
context:
space:
mode:
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3225-drm-amdgpu-fix-double-ucode-load-by-PSP-v3.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3225-drm-amdgpu-fix-double-ucode-load-by-PSP-v3.patch183
1 files changed, 183 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3225-drm-amdgpu-fix-double-ucode-load-by-PSP-v3.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3225-drm-amdgpu-fix-double-ucode-load-by-PSP-v3.patch
new file mode 100644
index 00000000..34ba31f3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3225-drm-amdgpu-fix-double-ucode-load-by-PSP-v3.patch
@@ -0,0 +1,183 @@
+From dfeb69f03e80ff120ec8d59b4a05e4593538a1c4 Mon Sep 17 00:00:00 2001
+From: Monk Liu <Monk.Liu@amd.com>
+Date: Wed, 31 Jul 2019 16:47:56 +0800
+Subject: [PATCH 3225/4256] drm/amdgpu: fix double ucode load by PSP(v3)
+
+previously the ucode loading of PSP was repreated, one executed in
+phase_1 init/re-init/resume and the other in fw_loading routine
+
+Avoid this double loading by clearing ip_blocks.status.hw in suspend or reset
+prior to the FW loading and any block's hw_init/resume
+
+v2:
+still do the smu fw loading since it is needed by bare-metal
+
+v3:
+drop the change in reinit_early_sriov, just clear all block's status.hw
+in the head place and set the status.hw after hw_init done is enough
+
+Signed-off-by: Monk Liu <Monk.Liu@amd.com>
+Reviewed-by: Emily Deng <Emily.Deng@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 59 ++++++++++++++--------
+ 1 file changed, 38 insertions(+), 21 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 111d3fc175d8..87179dd882d0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -1745,28 +1745,34 @@ static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
+
+ if (adev->asic_type >= CHIP_VEGA10) {
+ for (i = 0; i < adev->num_ip_blocks; i++) {
+- if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
+- if (adev->in_gpu_reset || adev->in_suspend) {
+- if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset)
+- break; /* sriov gpu reset, psp need to do hw_init before IH because of hw limit */
+- r = adev->ip_blocks[i].version->funcs->resume(adev);
+- if (r) {
+- DRM_ERROR("resume of IP block <%s> failed %d\n",
++ if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP)
++ continue;
++
++ /* no need to do the fw loading again if already done*/
++ if (adev->ip_blocks[i].status.hw == true)
++ break;
++
++ if (adev->in_gpu_reset || adev->in_suspend) {
++ r = adev->ip_blocks[i].version->funcs->resume(adev);
++ if (r) {
++ DRM_ERROR("resume of IP block <%s> failed %d\n",
+ adev->ip_blocks[i].version->funcs->name, r);
+- return r;
+- }
+- } else {
+- r = adev->ip_blocks[i].version->funcs->hw_init(adev);
+- if (r) {
+- DRM_ERROR("hw_init of IP block <%s> failed %d\n",
+- adev->ip_blocks[i].version->funcs->name, r);
+- return r;
+- }
++ return r;
++ }
++ } else {
++ r = adev->ip_blocks[i].version->funcs->hw_init(adev);
++ if (r) {
++ DRM_ERROR("hw_init of IP block <%s> failed %d\n",
++ adev->ip_blocks[i].version->funcs->name, r);
++ return r;
+ }
+- adev->ip_blocks[i].status.hw = true;
+ }
++
++ adev->ip_blocks[i].status.hw = true;
++ break;
+ }
+ }
++
+ r = amdgpu_pm_load_smu_firmware(adev, &smu_version);
+
+ return r;
+@@ -2200,7 +2206,9 @@ static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
+ if (r) {
+ DRM_ERROR("suspend of IP block <%s> failed %d\n",
+ adev->ip_blocks[i].version->funcs->name, r);
++ return r;
+ }
++ adev->ip_blocks[i].status.hw = false;
+ }
+ }
+
+@@ -2240,14 +2248,16 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
+ if (is_support_sw_smu(adev)) {
+ /* todo */
+ } else if (adev->powerplay.pp_funcs &&
+- adev->powerplay.pp_funcs->set_mp1_state) {
++ adev->powerplay.pp_funcs->set_mp1_state) {
+ r = adev->powerplay.pp_funcs->set_mp1_state(
+ adev->powerplay.pp_handle,
+ adev->mp1_state);
+ if (r) {
+ DRM_ERROR("SMC failed to set mp1 state %d, %d\n",
+ adev->mp1_state, r);
++ return r;
+ }
++ adev->ip_blocks[i].status.hw = false;
+ }
+ }
+ }
+@@ -2302,6 +2312,7 @@ static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
+ for (j = 0; j < adev->num_ip_blocks; j++) {
+ block = &adev->ip_blocks[j];
+
++ block->status.hw = false;
+ if (block->version->type != ip_order[i] ||
+ !block->status.valid)
+ continue;
+@@ -2310,6 +2321,7 @@ static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
+ DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
+ if (r)
+ return r;
++ block->status.hw = true;
+ }
+ }
+
+@@ -2337,13 +2349,15 @@ static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
+ block = &adev->ip_blocks[j];
+
+ if (block->version->type != ip_order[i] ||
+- !block->status.valid)
++ !block->status.valid ||
++ block->status.hw)
+ continue;
+
+ r = block->version->funcs->hw_init(adev);
+ DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
+ if (r)
+ return r;
++ block->status.hw = true;
+ }
+ }
+
+@@ -2367,17 +2381,19 @@ static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
+ int i, r;
+
+ for (i = 0; i < adev->num_ip_blocks; i++) {
+- if (!adev->ip_blocks[i].status.valid)
++ if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
+ continue;
+ if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
+ adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
+ adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
++
+ r = adev->ip_blocks[i].version->funcs->resume(adev);
+ if (r) {
+ DRM_ERROR("resume of IP block <%s> failed %d\n",
+ adev->ip_blocks[i].version->funcs->name, r);
+ return r;
+ }
++ adev->ip_blocks[i].status.hw = true;
+ }
+ }
+
+@@ -2402,7 +2418,7 @@ static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
+ int i, r;
+
+ for (i = 0; i < adev->num_ip_blocks; i++) {
+- if (!adev->ip_blocks[i].status.valid)
++ if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
+ continue;
+ if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
+ adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
+@@ -2415,6 +2431,7 @@ static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
+ adev->ip_blocks[i].version->funcs->name, r);
+ return r;
+ }
++ adev->ip_blocks[i].status.hw = true;
+ }
+
+ return 0;
+--
+2.17.1
+
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-04-25 00:06:15 +0000