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-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3209-drm-amdgpu-add-structures-for-umc-error-address-tran.patch52
1 files changed, 52 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3209-drm-amdgpu-add-structures-for-umc-error-address-tran.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3209-drm-amdgpu-add-structures-for-umc-error-address-tran.patch
new file mode 100644
index 00000000..db77869d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3209-drm-amdgpu-add-structures-for-umc-error-address-tran.patch
@@ -0,0 +1,52 @@
+From 9f38114f77a6ff68c3c59fb64e6f73439148c206 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Mon, 22 Jul 2019 18:30:59 +0800
+Subject: [PATCH 3209/4256] drm/amdgpu: add structures for umc error address
+ translation
+
+add related registers, callback function and channel index table
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h | 2 ++
+ drivers/gpu/drm/amd/amdgpu/umc_v6_1.c | 10 ++++++++++
+ 2 files changed, 12 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+index f5d6def96414..dfa1a39e57af 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+@@ -24,6 +24,8 @@
+ struct amdgpu_umc_funcs {
+ void (*query_ras_error_count)(struct amdgpu_device *adev,
+ void *ras_error_status);
++ void (*query_ras_error_address)(struct amdgpu_device *adev,
++ void *ras_error_status);
+ };
+
+ struct amdgpu_umc {
+diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+index 5b1ccb81b3a2..e05f3e68edb0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
++++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+@@ -29,6 +29,16 @@
+ #include "umc/umc_6_1_1_offset.h"
+ #include "umc/umc_6_1_1_sh_mask.h"
+
++#define smnMCA_UMC0_MCUMC_ADDRT0 0x50f10
++
++static uint32_t
++ umc_v6_1_channel_idx_tbl[UMC_V6_1_UMC_INSTANCE_NUM][UMC_V6_1_CHANNEL_INSTANCE_NUM] = {
++ {2, 18, 11, 27}, {4, 20, 13, 29},
++ {1, 17, 8, 24}, {7, 23, 14, 30},
++ {10, 26, 3, 19}, {12, 28, 5, 21},
++ {9, 25, 0, 16}, {15, 31, 6, 22}
++};
++
+ static void umc_v6_1_enable_umc_index_mode(struct amdgpu_device *adev,
+ uint32_t umc_instance)
+ {
+--
+2.17.1
+