diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3181-drm-amd-powerplay-correct-UVD-VCE-VCN-power-status-r.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3181-drm-amd-powerplay-correct-UVD-VCE-VCN-power-status-r.patch | 88 |
1 files changed, 88 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3181-drm-amd-powerplay-correct-UVD-VCE-VCN-power-status-r.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3181-drm-amd-powerplay-correct-UVD-VCE-VCN-power-status-r.patch new file mode 100644 index 00000000..8fb1fc15 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3181-drm-amd-powerplay-correct-UVD-VCE-VCN-power-status-r.patch @@ -0,0 +1,88 @@ +From 0288a2898fcdb948a8be9bd37a34828fbbb7798c Mon Sep 17 00:00:00 2001 +From: Evan Quan <evan.quan@amd.com> +Date: Mon, 22 Jul 2019 10:42:29 +0800 +Subject: [PATCH 3181/4256] drm/amd/powerplay: correct UVD/VCE/VCN power status + retrieval + +VCN should be used for Vega20 later ASICs while UVD and VCE +are for previous ASICs. + +Signed-off-by: Evan Quan <evan.quan@amd.com> +Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 56 +++++++++++++++++--------- + 1 file changed, 36 insertions(+), 20 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c +index 783cd0192d33..6cff61802400 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c +@@ -3070,28 +3070,44 @@ static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *a + if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size)) + seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64); + +- /* UVD clocks */ +- if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) { +- if (!value) { +- seq_printf(m, "UVD: Disabled\n"); +- } else { +- seq_printf(m, "UVD: Enabled\n"); +- if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size)) +- seq_printf(m, "\t%u MHz (DCLK)\n", value/100); +- if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size)) +- seq_printf(m, "\t%u MHz (VCLK)\n", value/100); ++ if (adev->asic_type > CHIP_VEGA20) { ++ /* VCN clocks */ ++ if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) { ++ if (!value) { ++ seq_printf(m, "VCN: Disabled\n"); ++ } else { ++ seq_printf(m, "VCN: Enabled\n"); ++ if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size)) ++ seq_printf(m, "\t%u MHz (DCLK)\n", value/100); ++ if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size)) ++ seq_printf(m, "\t%u MHz (VCLK)\n", value/100); ++ } + } +- } +- seq_printf(m, "\n"); ++ seq_printf(m, "\n"); ++ } else { ++ /* UVD clocks */ ++ if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) { ++ if (!value) { ++ seq_printf(m, "UVD: Disabled\n"); ++ } else { ++ seq_printf(m, "UVD: Enabled\n"); ++ if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size)) ++ seq_printf(m, "\t%u MHz (DCLK)\n", value/100); ++ if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size)) ++ seq_printf(m, "\t%u MHz (VCLK)\n", value/100); ++ } ++ } ++ seq_printf(m, "\n"); + +- /* VCE clocks */ +- if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) { +- if (!value) { +- seq_printf(m, "VCE: Disabled\n"); +- } else { +- seq_printf(m, "VCE: Enabled\n"); +- if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size)) +- seq_printf(m, "\t%u MHz (ECCLK)\n", value/100); ++ /* VCE clocks */ ++ if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) { ++ if (!value) { ++ seq_printf(m, "VCE: Disabled\n"); ++ } else { ++ seq_printf(m, "VCE: Enabled\n"); ++ if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size)) ++ seq_printf(m, "\t%u MHz (ECCLK)\n", value/100); ++ } + } + } + +-- +2.17.1 + |