diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3176-drm-amdgpu-update-more-sdma-instances-irq-support.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3176-drm-amdgpu-update-more-sdma-instances-irq-support.patch | 176 |
1 files changed, 176 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3176-drm-amdgpu-update-more-sdma-instances-irq-support.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3176-drm-amdgpu-update-more-sdma-instances-irq-support.patch new file mode 100644 index 00000000..91566d6e --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3176-drm-amdgpu-update-more-sdma-instances-irq-support.patch @@ -0,0 +1,176 @@ +From cd33457f0a0bd14fca5c2d6f1ec69795c8f2b4e1 Mon Sep 17 00:00:00 2001 +From: Le Ma <le.ma@amd.com> +Date: Tue, 16 Jul 2019 15:21:54 +0800 +Subject: [PATCH 3176/4256] drm/amdgpu: update more sdma instances irq support + +Update for sdma ras ecc_irq and other minors. + +Signed-off-by: Le Ma <le.ma@amd.com> +Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 77 +++++++++----------------- + 1 file changed, 27 insertions(+), 50 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +index 2ddeff86aaea..2876cdabef41 100644 +--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +@@ -295,7 +295,7 @@ static unsigned sdma_v4_0_seq_to_irq_id(int seq_num) + default: + break; + } +- return 0; ++ return -EINVAL; + } + + static int sdma_v4_0_irq_id_to_seq(unsigned client_id) +@@ -320,7 +320,7 @@ static int sdma_v4_0_irq_id_to_seq(unsigned client_id) + default: + break; + } +- return 0; ++ return -EINVAL; + } + + static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) +@@ -1645,7 +1645,7 @@ static int sdma_v4_0_late_init(void *handle) + .sub_block_index = 0, + .name = "sdma", + }; +- int r; ++ int r, i; + + if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { + amdgpu_ras_feature_enable_on_boot(adev, &ras_block, 0); +@@ -1702,14 +1702,11 @@ static int sdma_v4_0_late_init(void *handle) + if (r) + goto sysfs; + resume: +- r = amdgpu_irq_get(adev, &adev->sdma.ecc_irq, AMDGPU_SDMA_IRQ_INSTANCE0); +- if (r) +- goto irq; +- +- r = amdgpu_irq_get(adev, &adev->sdma.ecc_irq, AMDGPU_SDMA_IRQ_INSTANCE1); +- if (r) { +- amdgpu_irq_put(adev, &adev->sdma.ecc_irq, AMDGPU_SDMA_IRQ_INSTANCE0); +- goto irq; ++ for (i = 0; i < adev->sdma.num_instances; i++) { ++ r = amdgpu_irq_get(adev, &adev->sdma.ecc_irq, ++ sdma_v4_0_seq_to_irq_id(i)); ++ if (r) ++ goto irq; + } + + return 0; +@@ -1742,16 +1739,13 @@ static int sdma_v4_0_sw_init(void *handle) + } + + /* SDMA SRAM ECC event */ +- r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, SDMA0_4_0__SRCID__SDMA_SRAM_ECC, +- &adev->sdma.ecc_irq); +- if (r) +- return r; +- +- /* SDMA SRAM ECC event */ +- r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, SDMA1_4_0__SRCID__SDMA_SRAM_ECC, +- &adev->sdma.ecc_irq); +- if (r) +- return r; ++ for (i = 0; i < adev->sdma.num_instances; i++) { ++ r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), ++ SDMA0_4_0__SRCID__SDMA_SRAM_ECC, ++ &adev->sdma.ecc_irq); ++ if (r) ++ return r; ++ } + + for (i = 0; i < adev->sdma.num_instances; i++) { + ring = &adev->sdma.instance[i].ring; +@@ -1784,9 +1778,7 @@ static int sdma_v4_0_sw_init(void *handle) + sprintf(ring->name, "page%d", i); + r = amdgpu_ring_init(adev, ring, 1024, + &adev->sdma.trap_irq, +- (i == 0) ? +- AMDGPU_SDMA_IRQ_INSTANCE0 : +- AMDGPU_SDMA_IRQ_INSTANCE1); ++ AMDGPU_SDMA_IRQ_INSTANCE0 + i); + if (r) + return r; + } +@@ -1849,12 +1841,15 @@ static int sdma_v4_0_hw_init(void *handle) + static int sdma_v4_0_hw_fini(void *handle) + { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; ++ int i; + + if (amdgpu_sriov_vf(adev)) + return 0; + +- amdgpu_irq_put(adev, &adev->sdma.ecc_irq, AMDGPU_SDMA_IRQ_INSTANCE0); +- amdgpu_irq_put(adev, &adev->sdma.ecc_irq, AMDGPU_SDMA_IRQ_INSTANCE1); ++ for (i = 0; i < adev->sdma.num_instances; i++) { ++ amdgpu_irq_put(adev, &adev->sdma.ecc_irq, ++ sdma_v4_0_seq_to_irq_id(i)); ++ } + + sdma_v4_0_ctx_switch_enable(adev, false); + sdma_v4_0_enable(adev, false); +@@ -1968,16 +1963,9 @@ static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev, + { + uint32_t instance, err_source; + +- switch (entry->client_id) { +- case SOC15_IH_CLIENTID_SDMA0: +- instance = 0; +- break; +- case SOC15_IH_CLIENTID_SDMA1: +- instance = 1; +- break; +- default: ++ instance = sdma_v4_0_irq_id_to_seq(entry->client_id); ++ if (instance < 0) + return 0; +- } + + switch (entry->src_id) { + case SDMA0_4_0__SRCID__SDMA_SRAM_ECC: +@@ -2023,16 +2011,9 @@ static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev, + + DRM_ERROR("Illegal instruction in SDMA command stream\n"); + +- switch (entry->client_id) { +- case SOC15_IH_CLIENTID_SDMA0: +- instance = 0; +- break; +- case SOC15_IH_CLIENTID_SDMA1: +- instance = 1; +- break; +- default: ++ instance = sdma_v4_0_irq_id_to_seq(entry->client_id); ++ if (instance < 0) + return 0; +- } + + switch (entry->ring_id) { + case 0: +@@ -2049,14 +2030,10 @@ static int sdma_v4_0_set_ecc_irq_state(struct amdgpu_device *adev, + { + u32 sdma_edc_config; + +- u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ? +- sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_EDC_CONFIG) : +- sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_EDC_CONFIG); +- +- sdma_edc_config = RREG32(reg_offset); ++ sdma_edc_config = RREG32_SDMA(type, mmSDMA0_EDC_CONFIG); + sdma_edc_config = REG_SET_FIELD(sdma_edc_config, SDMA0_EDC_CONFIG, ECC_INT_ENABLE, + state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); +- WREG32(reg_offset, sdma_edc_config); ++ WREG32_SDMA(type, mmSDMA0_EDC_CONFIG, sdma_edc_config); + + return 0; + } +-- +2.17.1 + |