diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3160-drm-amd-display-Support-uclk-switching-for-DCN2.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3160-drm-amd-display-Support-uclk-switching-for-DCN2.patch | 78 |
1 files changed, 78 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3160-drm-amd-display-Support-uclk-switching-for-DCN2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3160-drm-amd-display-Support-uclk-switching-for-DCN2.patch new file mode 100644 index 00000000..3d89b372 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3160-drm-amd-display-Support-uclk-switching-for-DCN2.patch @@ -0,0 +1,78 @@ +From 4090dc5ab539ecba25b5ae156f34a32adb87b115 Mon Sep 17 00:00:00 2001 +From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> +Date: Tue, 30 Jul 2019 09:45:33 -0400 +Subject: [PATCH 3160/4256] drm/amd/display: Support uclk switching for DCN2 + +[Why] +We were previously forcing the uclk for every state to max and reducing +the switch time to prevent uclk switching from occuring. This workaround +was previously needed in order to avoid hangs + underflow under certain +display configurations. + +Now that DC has the proper fix complete we can drop the hacks and +improve power for most display configurations. + +[How] +We still need the function pointers hooked up to grab the real uclk +states from pplib. The rest of the prior hack can be reverted. + +The key requirements here are really just DC support, updated firmware, +and support for disabling p-state support when needed in pplib/smu. + +When these requirements are met uclk switching works without underflow +or hangs. + +Fixes: 02316e963a5a ("drm/amd/display: Force uclk to max for every state") + +Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> +Acked-by: Alex Deucher <alexander.deucher@amd.com> +Reviewed-by: Harry Wentland <harry.wentland@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 10 ---------- + 1 file changed, 10 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +index ff30f5cc4981..42d3666f2037 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +@@ -2817,9 +2817,6 @@ static void cap_soc_clocks( + && max_clocks.uClockInKhz != 0) + bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16; + +- // HACK: Force every uclk to max for now to "disable" uclk switching. +- bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16; +- + if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000)) + && max_clocks.fabricClockInKhz != 0) + bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000); +@@ -3035,8 +3032,6 @@ static bool init_soc_bounding_box(struct dc *dc, + le32_to_cpu(bb->vmm_page_size_bytes); + dcn2_0_soc.dram_clock_change_latency_us = + fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us); +- // HACK!! Lower uclock latency switch time so we don't switch +- dcn2_0_soc.dram_clock_change_latency_us = 10; + dcn2_0_soc.writeback_dram_clock_change_latency_us = + fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us); + dcn2_0_soc.return_bus_width_bytes = +@@ -3078,7 +3073,6 @@ static bool init_soc_bounding_box(struct dc *dc, + struct pp_smu_nv_clock_table max_clocks = {0}; + unsigned int uclk_states[8] = {0}; + unsigned int num_states = 0; +- int i; + enum pp_smu_status status; + bool clock_limits_available = false; + bool uclk_states_available = false; +@@ -3100,10 +3094,6 @@ static bool init_soc_bounding_box(struct dc *dc, + clock_limits_available = (status == PP_SMU_RESULT_OK); + } + +- // HACK: Use the max uclk_states value for all elements. +- for (i = 0; i < num_states; i++) +- uclk_states[i] = uclk_states[num_states - 1]; +- + if (clock_limits_available && uclk_states_available && num_states) + update_bounding_box(dc, &dcn2_0_soc, &max_clocks, uclk_states, num_states); + else if (clock_limits_available) +-- +2.17.1 + |