diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3159-drm-amd-display-Embed-DCN2-SOC-bounding-box.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3159-drm-amd-display-Embed-DCN2-SOC-bounding-box.patch | 162 |
1 files changed, 162 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3159-drm-amd-display-Embed-DCN2-SOC-bounding-box.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3159-drm-amd-display-Embed-DCN2-SOC-bounding-box.patch new file mode 100644 index 00000000..a76cef42 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3159-drm-amd-display-Embed-DCN2-SOC-bounding-box.patch @@ -0,0 +1,162 @@ +From 017e8e8e16a1527ce02507e8395482689b01783b Mon Sep 17 00:00:00 2001 +From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> +Date: Tue, 30 Jul 2019 09:08:34 -0400 +Subject: [PATCH 3159/4256] drm/amd/display: Embed DCN2 SOC bounding box + +[Why] +In order to support uclk switching on NV10 the SOC bounding box +needs to be updated. + +[How] +We currently read the constants from the gpu info FW, but supporting +workarounds in DC for different versions of the FW adds additional +complexity to the codebase. + +NV10 has been released so it's cleanest to keep the bounding box and +source code in sync by embedding the bounding box like we do for +other ASICs. + +Fixes: 02316e963a5a ("drm/amd/display: Force uclk to max for every state") + +Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> +Acked-by: Alex Deucher <alexander.deucher@amd.com> +Reviewed-by: Harry Wentland <harry.wentland@amd.com> +--- + .../drm/amd/display/dc/dcn20/dcn20_resource.c | 114 +++++++++++++++++- + 1 file changed, 112 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +index 44537651f0a1..ff30f5cc4981 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +@@ -80,7 +80,7 @@ + + #include "amdgpu_socbb.h" + +-#define SOC_BOUNDING_BOX_VALID false ++#define SOC_BOUNDING_BOX_VALID true + #define DC_LOGGER_INIT(logger) + + struct _vcs_dpi_ip_params_st dcn2_0_ip = { +@@ -154,7 +154,117 @@ struct _vcs_dpi_ip_params_st dcn2_0_ip = { + .xfc_fill_constant_bytes = 0, + }; + +-struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = { 0 }; ++struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = { ++ /* Defaults that get patched on driver load from firmware. */ ++ .clock_limits = { ++ { ++ .state = 0, ++ .dcfclk_mhz = 560.0, ++ .fabricclk_mhz = 560.0, ++ .dispclk_mhz = 513.0, ++ .dppclk_mhz = 513.0, ++ .phyclk_mhz = 540.0, ++ .socclk_mhz = 560.0, ++ .dscclk_mhz = 171.0, ++ .dram_speed_mts = 8960.0, ++ }, ++ { ++ .state = 1, ++ .dcfclk_mhz = 694.0, ++ .fabricclk_mhz = 694.0, ++ .dispclk_mhz = 642.0, ++ .dppclk_mhz = 642.0, ++ .phyclk_mhz = 600.0, ++ .socclk_mhz = 694.0, ++ .dscclk_mhz = 214.0, ++ .dram_speed_mts = 11104.0, ++ }, ++ { ++ .state = 2, ++ .dcfclk_mhz = 875.0, ++ .fabricclk_mhz = 875.0, ++ .dispclk_mhz = 734.0, ++ .dppclk_mhz = 734.0, ++ .phyclk_mhz = 810.0, ++ .socclk_mhz = 875.0, ++ .dscclk_mhz = 245.0, ++ .dram_speed_mts = 14000.0, ++ }, ++ { ++ .state = 3, ++ .dcfclk_mhz = 1000.0, ++ .fabricclk_mhz = 1000.0, ++ .dispclk_mhz = 1100.0, ++ .dppclk_mhz = 1100.0, ++ .phyclk_mhz = 810.0, ++ .socclk_mhz = 1000.0, ++ .dscclk_mhz = 367.0, ++ .dram_speed_mts = 16000.0, ++ }, ++ { ++ .state = 4, ++ .dcfclk_mhz = 1200.0, ++ .fabricclk_mhz = 1200.0, ++ .dispclk_mhz = 1284.0, ++ .dppclk_mhz = 1284.0, ++ .phyclk_mhz = 810.0, ++ .socclk_mhz = 1200.0, ++ .dscclk_mhz = 428.0, ++ .dram_speed_mts = 16000.0, ++ }, ++ /*Extra state, no dispclk ramping*/ ++ { ++ .state = 5, ++ .dcfclk_mhz = 1200.0, ++ .fabricclk_mhz = 1200.0, ++ .dispclk_mhz = 1284.0, ++ .dppclk_mhz = 1284.0, ++ .phyclk_mhz = 810.0, ++ .socclk_mhz = 1200.0, ++ .dscclk_mhz = 428.0, ++ .dram_speed_mts = 16000.0, ++ }, ++ }, ++ .num_states = 5, ++ .sr_exit_time_us = 8.6, ++ .sr_enter_plus_exit_time_us = 10.9, ++ .urgent_latency_us = 4.0, ++ .urgent_latency_pixel_data_only_us = 4.0, ++ .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, ++ .urgent_latency_vm_data_only_us = 4.0, ++ .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, ++ .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, ++ .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, ++ .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0, ++ .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0, ++ .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, ++ .max_avg_sdp_bw_use_normal_percent = 40.0, ++ .max_avg_dram_bw_use_normal_percent = 40.0, ++ .writeback_latency_us = 12.0, ++ .ideal_dram_bw_after_urgent_percent = 40.0, ++ .max_request_size_bytes = 256, ++ .dram_channel_width_bytes = 2, ++ .fabric_datapath_to_dcn_data_return_bytes = 64, ++ .dcn_downspread_percent = 0.5, ++ .downspread_percent = 0.38, ++ .dram_page_open_time_ns = 50.0, ++ .dram_rw_turnaround_time_ns = 17.5, ++ .dram_return_buffer_per_channel_bytes = 8192, ++ .round_trip_ping_latency_dcfclk_cycles = 131, ++ .urgent_out_of_order_return_per_channel_bytes = 256, ++ .channel_interleave_bytes = 256, ++ .num_banks = 8, ++ .num_chans = 16, ++ .vmm_page_size_bytes = 4096, ++ .dram_clock_change_latency_us = 404.0, ++ .dummy_pstate_latency_us = 5.0, ++ .writeback_dram_clock_change_latency_us = 23.0, ++ .return_bus_width_bytes = 64, ++ .dispclk_dppclk_vco_speed_mhz = 3850, ++ .xfc_bus_transport_time_us = 20, ++ .xfc_xbuf_latency_tolerance_us = 4, ++ .use_urgent_burst_bw = 0 ++}; + + + #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL +-- +2.17.1 + |