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-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3144-drm-amdgpu-Default-disable-GDS-for-compute-gfx.patch219
1 files changed, 219 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3144-drm-amdgpu-Default-disable-GDS-for-compute-gfx.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3144-drm-amdgpu-Default-disable-GDS-for-compute-gfx.patch
new file mode 100644
index 00000000..60233c15
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3144-drm-amdgpu-Default-disable-GDS-for-compute-gfx.patch
@@ -0,0 +1,219 @@
+From 8d4a229f773bc4e574b7877ce26544272db4b0f7 Mon Sep 17 00:00:00 2001
+From: Joseph Greathouse <Joseph.Greathouse@amd.com>
+Date: Fri, 26 Jul 2019 15:52:05 -0500
+Subject: [PATCH 3144/4256] drm/amdgpu: Default disable GDS for compute+gfx
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Units in the GDS block default to allowing all VMIDs access to all
+entries. Disable shader access to the GDS, GWS, and OA blocks from all
+compute and gfx VMIDs by default. For compute, HWS firmware will set
+up the access bits for the appropriate VMID when a compute queue
+requires access to these blocks.
+The driver will handle enabling access on-demand for graphics VMIDs.
+
+Leaving VMID0 with full access because otherwise HWS cannot save or
+restore values during task switch.
+
+v2: Fixed code and comment styling.
+
+Change-Id: I5b8cf2023b79480555dc909019f062c3c7e37241
+Signed-off-by: Joseph Greathouse <Joseph.Greathouse@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 25 ++++++++++++++++-------
+ drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 24 +++++++++++++++-------
+ drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 24 +++++++++++++++-------
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 28 +++++++++++++++++---------
+ 4 files changed, 71 insertions(+), 30 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 23ed5b2dae19..3df1e6212123 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -1516,17 +1516,27 @@ static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
+ }
+ nv_grbm_select(adev, 0, 0, 0, 0);
+ mutex_unlock(&adev->srbm_mutex);
++}
+
+- /* Initialize all compute VMIDs to have no GDS, GWS, or OA
+- acccess. These should be enabled by FW for target VMIDs. */
+- for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
+- WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
+- WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
+- WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
+- WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
++static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
++{
++ int vmid;
++
++ /*
++ * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
++ * access. Compute VMIDs should be enabled by FW for target VMIDs,
++ * the driver can enable them for graphics. VMID0 should maintain
++ * access so that HWS firmware can save/restore entries.
++ */
++ for (vmid = 1; vmid < 16; vmid++) {
++ WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
++ WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
++ WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
++ WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
+ }
+ }
+
++
+ static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
+ {
+ int i, j, k;
+@@ -1629,6 +1639,7 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
+ mutex_unlock(&adev->srbm_mutex);
+
+ gfx_v10_0_init_compute_vmid(adev);
++ gfx_v10_0_init_gds_vmid(adev);
+
+ }
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+index 3f98624772a4..48796b6824cf 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+@@ -1877,14 +1877,23 @@ static void gfx_v7_0_init_compute_vmid(struct amdgpu_device *adev)
+ }
+ cik_srbm_select(adev, 0, 0, 0, 0);
+ mutex_unlock(&adev->srbm_mutex);
++}
+
+- /* Initialize all compute VMIDs to have no GDS, GWS, or OA
+- acccess. These should be enabled by FW for target VMIDs. */
+- for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
+- WREG32(amdgpu_gds_reg_offset[i].mem_base, 0);
+- WREG32(amdgpu_gds_reg_offset[i].mem_size, 0);
+- WREG32(amdgpu_gds_reg_offset[i].gws, 0);
+- WREG32(amdgpu_gds_reg_offset[i].oa, 0);
++static void gfx_v7_0_init_gds_vmid(struct amdgpu_device *adev)
++{
++ int vmid;
++
++ /*
++ * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
++ * access. Compute VMIDs should be enabled by FW for target VMIDs,
++ * the driver can enable them for graphics. VMID0 should maintain
++ * access so that HWS firmware can save/restore entries.
++ */
++ for (vmid = 1; vmid < 16; vmid++) {
++ WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0);
++ WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0);
++ WREG32(amdgpu_gds_reg_offset[vmid].gws, 0);
++ WREG32(amdgpu_gds_reg_offset[vmid].oa, 0);
+ }
+ }
+
+@@ -1966,6 +1975,7 @@ static void gfx_v7_0_constants_init(struct amdgpu_device *adev)
+ mutex_unlock(&adev->srbm_mutex);
+
+ gfx_v7_0_init_compute_vmid(adev);
++ gfx_v7_0_init_gds_vmid(adev);
+
+ WREG32(mmSX_DEBUG_1, 0x20);
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+index a18d8ab1e4b2..79ccc4bfb676 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+@@ -3702,14 +3702,23 @@ static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
+ }
+ vi_srbm_select(adev, 0, 0, 0, 0);
+ mutex_unlock(&adev->srbm_mutex);
++}
+
+- /* Initialize all compute VMIDs to have no GDS, GWS, or OA
+- acccess. These should be enabled by FW for target VMIDs. */
+- for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
+- WREG32(amdgpu_gds_reg_offset[i].mem_base, 0);
+- WREG32(amdgpu_gds_reg_offset[i].mem_size, 0);
+- WREG32(amdgpu_gds_reg_offset[i].gws, 0);
+- WREG32(amdgpu_gds_reg_offset[i].oa, 0);
++static void gfx_v8_0_init_gds_vmid(struct amdgpu_device *adev)
++{
++ int vmid;
++
++ /*
++ * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
++ * access. Compute VMIDs should be enabled by FW for target VMIDs,
++ * the driver can enable them for graphics. VMID0 should maintain
++ * access so that HWS firmware can save/restore entries.
++ */
++ for (vmid = 1; vmid < 16; vmid++) {
++ WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0);
++ WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0);
++ WREG32(amdgpu_gds_reg_offset[vmid].gws, 0);
++ WREG32(amdgpu_gds_reg_offset[vmid].oa, 0);
+ }
+ }
+
+@@ -3779,6 +3788,7 @@ static void gfx_v8_0_constants_init(struct amdgpu_device *adev)
+ mutex_unlock(&adev->srbm_mutex);
+
+ gfx_v8_0_init_compute_vmid(adev);
++ gfx_v8_0_init_gds_vmid(adev);
+
+ mutex_lock(&adev->grbm_idx_mutex);
+ /*
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 45d5919b0cd5..1b24a338cbdf 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -2030,15 +2030,6 @@ static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
+ }
+ soc15_grbm_select(adev, 0, 0, 0, 0);
+ mutex_unlock(&adev->srbm_mutex);
+-
+- /* Initialize all compute VMIDs to have no GDS, GWS, or OA
+- acccess. These should be enabled by FW for target VMIDs. */
+- for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
+- WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
+- WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
+- WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
+- WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
+- }
+ data = 0;
+ data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG,
+ VMID_SEL, trap_config_vmid_mask);
+@@ -2047,6 +2038,24 @@ static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data);
+ }
+
++static void gfx_v9_0_init_gds_vmid(struct amdgpu_device *adev)
++{
++ int vmid;
++
++ /*
++ * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
++ * access. Compute VMIDs should be enabled by FW for target VMIDs,
++ * the driver can enable them for graphics. VMID0 should maintain
++ * access so that HWS firmware can save/restore entries.
++ */
++ for (vmid = 1; vmid < 16; vmid++) {
++ WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
++ WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
++ WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
++ WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
++ }
++}
++
+ static void gfx_v9_0_constants_init(struct amdgpu_device *adev)
+ {
+ u32 tmp;
+@@ -2091,6 +2100,7 @@ static void gfx_v9_0_constants_init(struct amdgpu_device *adev)
+ mutex_unlock(&adev->srbm_mutex);
+
+ gfx_v9_0_init_compute_vmid(adev);
++ gfx_v9_0_init_gds_vmid(adev);
+ }
+
+ static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
+--
+2.17.1
+
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-04-24 21:05:01 +0000