diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3124-drm-amdgpu-Add-check-for-USWC-support-for-amdgpu_dis.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3124-drm-amdgpu-Add-check-for-USWC-support-for-amdgpu_dis.patch | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3124-drm-amdgpu-Add-check-for-USWC-support-for-amdgpu_dis.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3124-drm-amdgpu-Add-check-for-USWC-support-for-amdgpu_dis.patch new file mode 100644 index 00000000..2058ca82 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3124-drm-amdgpu-Add-check-for-USWC-support-for-amdgpu_dis.patch @@ -0,0 +1,42 @@ +From cc71845f9c18fb982846fe21719ebebd6adff312 Mon Sep 17 00:00:00 2001 +From: Andrey Grodzovsky <andrey.grodzovsky@amd.com> +Date: Wed, 24 Jul 2019 11:09:03 -0400 +Subject: [PATCH 3124/4256] drm/amdgpu: Add check for USWC support for + amdgpu_display_supported_domains +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This verifies we don't add GTT as allowed domnain for APUs when USWC +is disabled. + +Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> +Acked-by: Michel Dänzer <michel.daenzer@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 9 ++++++++- + 1 file changed, 8 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +index 36da6372607b..86bb15f83dcc 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +@@ -498,8 +498,15 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev) + uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; + + #if defined(CONFIG_DRM_AMD_DC) ++ /* ++ * if amdgpu_bo_validate_uswc returns false it means that USWC mappings ++ * is not supported for this board. But this mapping is required ++ * to avoid hang caused by placement of scanout BO in GTT on certain ++ * APUs. So force the BO placement to VRAM in case this architecture ++ * will not allow USWC mappings. ++ */ + if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type < CHIP_RAVEN && +- adev->flags & AMD_IS_APU && ++ adev->flags & AMD_IS_APU && amdgpu_bo_support_uswc(0) && + amdgpu_device_asic_has_dc_support(adev->asic_type)) + domain |= AMDGPU_GEM_DOMAIN_GTT; + #endif +-- +2.17.1 + |