diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3076-drm-amd-display-use-min-disp-and-dpp-clk-debug-optio.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3076-drm-amd-display-use-min-disp-and-dpp-clk-debug-optio.patch | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3076-drm-amd-display-use-min-disp-and-dpp-clk-debug-optio.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3076-drm-amd-display-use-min-disp-and-dpp-clk-debug-optio.patch new file mode 100644 index 00000000..049798a1 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3076-drm-amd-display-use-min-disp-and-dpp-clk-debug-optio.patch @@ -0,0 +1,58 @@ +From 377dd6145f4f34175ad5dc359a147391a7b0d4d8 Mon Sep 17 00:00:00 2001 +From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Date: Tue, 2 Jul 2019 14:51:01 -0400 +Subject: [PATCH 3076/4256] drm/amd/display: use min disp and dpp clk debug + option for dcn2 + +This allows to set a minimum display and dpp clock on dcn2+ HW +by adjusting clocks used for dml calculations. + +Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Leo Li <sunpeng.li@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dc.h | 1 + + drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 8 ++++---- + 2 files changed, 5 insertions(+), 4 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h +index fded67795e73..df06b41dcd5e 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc.h ++++ b/drivers/gpu/drm/amd/display/dc/dc.h +@@ -347,6 +347,7 @@ struct dc_debug_options { + bool disable_pplib_wm_range; + enum wm_report_mode pplib_wm_report_mode; + unsigned int min_disp_clk_khz; ++ unsigned int min_dpp_clk_khz; + int sr_exit_time_dpm0_ns; + int sr_enter_plus_exit_time_dpm0_ns; + int sr_exit_time_ns; +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +index 158743b165e8..5571b8bfc942 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +@@ -2168,10 +2168,6 @@ bool dcn20_fast_validate_bw( + } + if (force_split && context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 1) + context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] /= 2; +- if (dc->config.forced_clocks == true) { +- context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] = +- context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; +- } + if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { + hsplit_pipe = find_idle_secondary_pipe(&context->res_ctx, dc->res_pool, pipe); + ASSERT(hsplit_pipe); +@@ -2291,6 +2287,10 @@ void dcn20_calculate_wm( + pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; + pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; + } ++ if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000) ++ pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; ++ if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000) ++ pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; + + pipe_cnt++; + } +-- +2.17.1 + |