diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3075-drm-amd-display-add-a-option-to-force-the-clock-at-e.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3075-drm-amd-display-add-a-option-to-force-the-clock-at-e.patch | 61 |
1 files changed, 61 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3075-drm-amd-display-add-a-option-to-force-the-clock-at-e.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3075-drm-amd-display-add-a-option-to-force-the-clock-at-e.patch new file mode 100644 index 00000000..a59bcc5a --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3075-drm-amd-display-add-a-option-to-force-the-clock-at-e.patch @@ -0,0 +1,61 @@ +From 8ab65fac8b5810dedc0c1f4a0cf599b43cd67179 Mon Sep 17 00:00:00 2001 +From: Charlene Liu <charlene.liu@amd.com> +Date: Tue, 2 Jul 2019 14:04:35 -0400 +Subject: [PATCH 3075/4256] drm/amd/display: add a option to force the clock at + every mode change. + +[Description] +This is for HW negative stress testing use. +force reset the dispclk and dppclk even the same clock already set in HW. + +Signed-off-by: Charlene Liu <charlene.liu@amd.com> +Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Acked-by: Leo Li <sunpeng.li@amd.com> +--- + .../gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 9 ++++++++- + drivers/gpu/drm/amd/display/dc/dc.h | 1 + + 2 files changed, 9 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c +index 9a873e2b3736..3cff4f0518d3 100644 +--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c ++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c +@@ -151,7 +151,14 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base, + bool enter_display_off = false; + bool dpp_clock_lowered = false; + struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; ++ bool force_reset = false; + ++ if (clk_mgr_base->clks.dispclk_khz == 0 || ++ dc->debug.force_clock_mode & 0x1) { ++ //this is from resume or boot up, if forced_clock cfg option used, we bypass program dispclk and DPPCLK, but need set them for S3. ++ force_reset = true; ++ //force_clock_mode 0x1: force reset the clock even it is the same clock as long as it is in Passive level. ++ } + display_count = clk_mgr_helper_get_active_display_cnt(dc, context); + if (dc->res_pool->pp_smu) + pp_smu = &dc->res_pool->pp_smu->nv_funcs; +@@ -223,7 +230,7 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base, + + update_dispclk = true; + } +- if (dc->config.forced_clocks == false) { ++ if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) { + if (dpp_clock_lowered) { + // if clock is being lowered, increase DTO before lowering refclk + dcn20_update_clocks_update_dpp_dto(clk_mgr, context); +diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h +index 79827884cd80..fded67795e73 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc.h ++++ b/drivers/gpu/drm/amd/display/dc/dc.h +@@ -388,6 +388,7 @@ struct dc_debug_options { + #if defined(CONFIG_DRM_AMD_DC_DCN2_0) + bool cm_in_bypass; + #endif ++ int force_clock_mode;/*every mode change.*/ + }; + + struct dc_debug_data { +-- +2.17.1 + |