diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3066-drm-amd-display-Add-DIG_CLOCK_PATTERN-register.patch')
-rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3066-drm-amd-display-Add-DIG_CLOCK_PATTERN-register.patch | 59 |
1 files changed, 59 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3066-drm-amd-display-Add-DIG_CLOCK_PATTERN-register.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3066-drm-amd-display-Add-DIG_CLOCK_PATTERN-register.patch new file mode 100644 index 00000000..16d3e8b9 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3066-drm-amd-display-Add-DIG_CLOCK_PATTERN-register.patch @@ -0,0 +1,59 @@ +From 164d9d908d610e980513d9bcd2dac1b760575aae Mon Sep 17 00:00:00 2001 +From: Nevenko Stupar <Nevenko.Stupar@amd.com> +Date: Fri, 28 Jun 2019 12:12:13 -0400 +Subject: [PATCH 3066/4256] drm/amd/display: Add DIG_CLOCK_PATTERN register + +Add this register for future use + +Signed-off-by: Nevenko Stupar <Nevenko.Stupar@amd.com> +Reviewed-by: Vitaly Prosyak <vitaly.prosyak@amd.com> +Acked-by: Leo Li <sunpeng.li@amd.com> +--- + .../drm/amd/display/dc/dcn10/dcn10_stream_encoder.h | 10 +++++++--- + 1 file changed, 7 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h +index ab0ead3c3f46..f585e7b620cc 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h +@@ -89,7 +89,8 @@ + SRI(DP_VID_STREAM_CNTL, DP, id), \ + SRI(DP_VID_TIMING, DP, id), \ + SRI(DP_SEC_AUD_N, DP, id), \ +- SRI(DP_SEC_TIMESTAMP, DP, id) ++ SRI(DP_SEC_TIMESTAMP, DP, id), \ ++ SRI(DIG_CLOCK_PATTERN, DIG, id) + + #define SE_DCN_REG_LIST(id)\ + SE_COMMON_DCN_REG_LIST(id) +@@ -170,6 +171,7 @@ struct dcn10_stream_enc_registers { + uint32_t HDMI_METADATA_PACKET_CONTROL; + uint32_t DP_SEC_FRAMING4; + #endif ++ uint32_t DIG_CLOCK_PATTERN; + }; + + +@@ -298,7 +300,8 @@ struct dcn10_stream_enc_registers { + SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_VHEIGHT, mask_sh),\ + SE_SF(DIG0_HDMI_DB_CONTROL, HDMI_DB_DISABLE, mask_sh),\ + SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh),\ +- SE_SF(DIG0_DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh) ++ SE_SF(DIG0_DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh),\ ++ SE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh) + + #define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\ + SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) +@@ -460,7 +463,8 @@ struct dcn10_stream_enc_registers { + type HDMI_DB_DISABLE;\ + type DP_VID_N_MUL;\ + type DP_VID_M_DOUBLE_VALUE_EN;\ +- type DIG_SOURCE_SELECT ++ type DIG_SOURCE_SELECT;\ ++ type DIG_CLOCK_PATTERN + + #if defined(CONFIG_DRM_AMD_DC_DCN2_0) + #define SE_REG_FIELD_LIST_DCN2_0(type) \ +-- +2.17.1 + |