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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3033-drm-amd-display-add-hdmi2.1-dsc-pps-packet-programmi.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3033-drm-amd-display-add-hdmi2.1-dsc-pps-packet-programmi.patch141
1 files changed, 141 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3033-drm-amd-display-add-hdmi2.1-dsc-pps-packet-programmi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3033-drm-amd-display-add-hdmi2.1-dsc-pps-packet-programmi.patch
new file mode 100644
index 00000000..1d66c947
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3033-drm-amd-display-add-hdmi2.1-dsc-pps-packet-programmi.patch
@@ -0,0 +1,141 @@
+From 94a92a427e633a38290cef3bcb504204e67a6eea Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Wed, 5 Jun 2019 16:35:08 -0400
+Subject: [PATCH 3033/4256] drm/amd/display: add hdmi2.1 dsc pps packet
+ programming
+
+This change adds EMP packet programming for enabling dsc with
+hdmi. The packets are structured according to VESA HDMI 2.1x
+r2 spec, section 10.10.2.2.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 14 +++++++-------
+ drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 13 ++++++-------
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 3 ++-
+ drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h | 1 +
+ 4 files changed, 16 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index 551fff68a5dc..168b853434d7 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -2769,10 +2769,10 @@ void core_link_enable_stream(
+ allocate_mst_payload(pipe_ctx);
+
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+- if (pipe_ctx->stream->timing.flags.DSC &&
+- (dc_is_dp_signal(pipe_ctx->stream->signal) ||
+- dc_is_virtual_signal(pipe_ctx->stream->signal))) {
+- dp_set_dsc_enable(pipe_ctx, true);
++ if (pipe_ctx->stream->timing.flags.DSC) {
++ if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
++ dc_is_virtual_signal(pipe_ctx->stream->signal))
++ dp_set_dsc_enable(pipe_ctx, true);
+ pipe_ctx->stream_res.tg->funcs->wait_for_state(
+ pipe_ctx->stream_res.tg,
+ CRTC_STATE_VBLANK);
+@@ -2833,9 +2833,9 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option)
+
+ disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+- if (pipe_ctx->stream->timing.flags.DSC &&
+- dc_is_dp_signal(pipe_ctx->stream->signal)) {
+- dp_set_dsc_enable(pipe_ctx, false);
++ if (pipe_ctx->stream->timing.flags.DSC) {
++ if (dc_is_dp_signal(pipe_ctx->stream->signal))
++ dp_set_dsc_enable(pipe_ctx, false);
+ }
+ #endif
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+index 211fadefe2f5..46257f0fcbe7 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+@@ -396,7 +396,7 @@ static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable)
+
+ /* This has to be done after DSC was enabled on RX first, i.e. after dp_enable_dsc_on_rx() had been called
+ */
+-static void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
++void set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
+ {
+ struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
+ struct dc *core_dc = pipe_ctx->stream->ctx->dc;
+@@ -435,7 +435,7 @@ static void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
+
+ dsc_optc_config_log(dsc, &dsc_optc_cfg);
+ /* Enable DSC in encoder */
+- if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment) && pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config)
++ if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment))
+ pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc,
+ optc_dsc_mode,
+ dsc_optc_cfg.bytes_per_pixel,
+@@ -454,11 +454,10 @@ static void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
+ OPTC_DSC_DISABLED, 0, 0);
+
+ /* disable DSC in stream encoder */
+- if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
++ if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment))
+ pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(
+ pipe_ctx->stream_res.stream_enc,
+ OPTC_DSC_DISABLED, 0, 0, NULL);
+- }
+
+ /* disable DSC block */
+ pipe_ctx->stream_res.dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc);
+@@ -479,12 +478,12 @@ bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable)
+
+ if (enable) {
+ if (dp_set_dsc_on_rx(pipe_ctx, true)) {
+- dp_set_dsc_on_stream(pipe_ctx, true);
++ set_dsc_on_stream(pipe_ctx, true);
+ result = true;
+ }
+ } else {
+ dp_set_dsc_on_rx(pipe_ctx, false);
+- dp_set_dsc_on_stream(pipe_ctx, false);
++ set_dsc_on_stream(pipe_ctx, false);
+ result = true;
+ }
+ out:
+@@ -500,7 +499,7 @@ bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx)
+ if (!dsc)
+ return false;
+
+- dp_set_dsc_on_stream(pipe_ctx, true);
++ set_dsc_on_stream(pipe_ctx, true);
+ return true;
+ }
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 7c08f81000c5..db57c2a99a15 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -1758,8 +1758,9 @@ static void dcn20_reset_back_end_for_pipe(
+ }
+ }
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+- else if (pipe_ctx->stream_res.dsc)
++ else if (pipe_ctx->stream_res.dsc) {
+ dp_set_dsc_enable(pipe_ctx, false);
++ }
+ #endif
+
+ /* by upper caller loop, parent pipe: pipe0, will be reset last.
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+index 2d95eff94239..c5293f9508fa 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+@@ -66,6 +66,7 @@ void dp_enable_mst_on_sink(struct dc_link *link, bool enable);
+ void dp_set_fec_ready(struct dc_link *link, bool ready);
+ void dp_set_fec_enable(struct dc_link *link, bool enable);
+ bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable);
++void set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);
+ bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx);
+ #endif
+
+--
+2.17.1
+
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-04-19 22:04:25 +0000