diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3025-drm-amd-display-Split-out-common-HUBP-registers-and-.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3025-drm-amd-display-Split-out-common-HUBP-registers-and-.patch | 342 |
1 files changed, 342 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3025-drm-amd-display-Split-out-common-HUBP-registers-and-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3025-drm-amd-display-Split-out-common-HUBP-registers-and-.patch new file mode 100644 index 00000000..4d4ca082 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3025-drm-amd-display-Split-out-common-HUBP-registers-and-.patch @@ -0,0 +1,342 @@ +From 9a458db365cb2222f2c6e0417630ce8eb7829622 Mon Sep 17 00:00:00 2001 +From: Charlene Liu <charlene.liu@amd.com> +Date: Wed, 5 Jun 2019 15:21:03 -0400 +Subject: [PATCH 3025/4256] drm/amd/display: Split out common HUBP registers + and code + +There are shared regs and code across DCN generations. Pull them out +into a shared common location. + +Also, expose some dcn20 init functions. + +Signed-off-by: Charlene Liu <charlene.liu@amd.com> +Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Acked-by: Leo Li <sunpeng.li@amd.com> +--- + .../gpu/drm/amd/display/dc/dce/dce_hwseq.h | 3 +- + .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 50 ++++++++++++------- + .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h | 23 ++++++--- + .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h | 23 +++++---- + .../drm/amd/display/dc/dcn20/dcn20_hwseq.c | 43 +++++++++++++++- + .../drm/amd/display/dc/dcn20/dcn20_hwseq.h | 14 ++---- + 6 files changed, 109 insertions(+), 47 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +index cb0a037b1c4a..3a49f1ffb5dd 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +@@ -696,7 +696,8 @@ struct dce_hwseq_registers { + type D2VGA_MODE_ENABLE; \ + type D3VGA_MODE_ENABLE; \ + type D4VGA_MODE_ENABLE; \ +- type AZALIA_AUDIO_DTO_MODULE; ++ type AZALIA_AUDIO_DTO_MODULE;\ ++ type HPO_HDMISTREAMCLK_GATE_DIS; + + struct dce_hwseq_shift { + HWSEQ_REG_FIELD_LIST(uint8_t) +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c +index 934bacc0c6ad..a16128814d62 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c +@@ -843,7 +843,7 @@ void min_set_viewport( + PRI_VIEWPORT_Y_START_C, viewport_c->y); + } + +-void hubp1_read_state(struct hubp *hubp) ++void hubp1_read_state_common(struct hubp *hubp) + { + struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); + struct dcn_hubp_state *s = &hubp1->state; +@@ -859,24 +859,6 @@ void hubp1_read_state(struct hubp *hubp) + PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode, + MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode, + CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode); +- REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, +- CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size, +- MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size, +- META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size, +- MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size, +- DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size, +- MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size, +- SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height, +- PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear); +- REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C, +- CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size, +- MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size, +- META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size, +- MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size, +- DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size, +- MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size, +- SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height, +- PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear); + + /* DLG - Per hubp */ + REG_GET_2(BLANK_OFFSET_0, +@@ -1030,8 +1012,38 @@ void hubp1_read_state(struct hubp *hubp) + REG_GET_2(DCN_TTU_QOS_WM, + QoS_LEVEL_LOW_WM, &s->qos_level_low_wm, + QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm); ++ + } + ++void hubp1_read_state(struct hubp *hubp) ++{ ++ struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); ++ struct dcn_hubp_state *s = &hubp1->state; ++ struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; ++ ++ hubp1_read_state_common(hubp); ++ ++ REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, ++ CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size, ++ MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size, ++ META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size, ++ MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size, ++ DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size, ++ MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size, ++ SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height, ++ PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear); ++ ++ REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C, ++ CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size, ++ MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size, ++ META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size, ++ MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size, ++ DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size, ++ MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size, ++ SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height, ++ PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear); ++ ++} + enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch) + { + enum cursor_pitch hw_pitch; +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h +index 31c8fdd3206c..8f4bcdc74116 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h +@@ -249,7 +249,8 @@ + .field_name = reg_name ## __ ## field_name ## post_fix + + /* Mask/shift struct generation macro for all ASICs (including those with reduced functionality) */ +-#define HUBP_MASK_SH_LIST_DCN_COMMON(mask_sh)\ ++/*1.x, 2.x, and 3.x*/ ++#define HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh)\ + HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_STATUS, mask_sh),\ +@@ -265,7 +266,6 @@ + HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, MAX_COMPRESSED_FRAGS, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, META_LINEAR, mask_sh),\ +- HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, PIPE_ALIGNED, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, META_PITCH, mask_sh),\ +@@ -372,12 +372,17 @@ + HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\ + HUBP_SF(HUBP0_HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh) +- +-#define HUBP_MASK_SH_LIST_DCN(mask_sh)\ +- HUBP_MASK_SH_LIST_DCN_COMMON(mask_sh),\ ++/*2.x and 1.x only*/ ++#define HUBP_MASK_SH_LIST_DCN_COMMON(mask_sh)\ ++ HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh),\ ++ HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh) + ++/*2.x and 1.x only*/ ++#define HUBP_MASK_SH_LIST_DCN(mask_sh)\ ++ HUBP_MASK_SH_LIST_DCN_COMMON(mask_sh) ++ + /* Mask/shift struct generation macro for ASICs with VM */ + #define HUBP_MASK_SH_LIST_DCN_VM(mask_sh)\ + HUBP_SF(HUBPREQ0_NOM_PARAMETERS_0, DST_Y_PER_PTE_ROW_NOM_L, mask_sh),\ +@@ -434,7 +439,7 @@ + HUBP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \ + HUBP_SF(CURSOR0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh) + +-#define DCN_HUBP_REG_FIELD_LIST(type) \ ++#define DCN_HUBP_REG_FIELD_BASE_LIST(type) \ + type HUBP_BLANK_EN;\ + type HUBP_DISABLE;\ + type HUBP_TTU_DISABLE;\ +@@ -459,7 +464,6 @@ + type ROTATION_ANGLE;\ + type H_MIRROR_EN;\ + type SURFACE_PIXEL_FORMAT;\ +- type ALPHA_PLANE_EN;\ + type SURFACE_FLIP_TYPE;\ + type SURFACE_FLIP_MODE_FOR_STEREOSYNC;\ + type SURFACE_FLIP_IN_STEREOSYNC;\ +@@ -632,6 +636,10 @@ + type CURSOR_DST_X_OFFSET; \ + type OUTPUT_FP + ++#define DCN_HUBP_REG_FIELD_LIST(type) \ ++ DCN_HUBP_REG_FIELD_BASE_LIST(type);\ ++ type ALPHA_PLANE_EN ++ + struct dcn_mi_registers { + HUBP_COMMON_REG_VARIABLE_LIST; + }; +@@ -760,5 +768,6 @@ void hubp1_vready_workaround(struct hubp *hubp, + struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest); + + void hubp1_init(struct hubp *hubp); ++void hubp1_read_state_common(struct hubp *hubp); + + #endif +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h +index d5acc348be22..2c6405a62fc1 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h +@@ -72,8 +72,8 @@ + SR(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\ + SR(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB) + +-#define HUBP_MASK_SH_LIST_DCN2_COMMON(mask_sh)\ +- HUBP_MASK_SH_LIST_DCN(mask_sh),\ ++#define HUBP_MASK_SH_LIST_DCN2_SHARE_COMMON(mask_sh)\ ++ HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh),\ + HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\ + HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\ +@@ -127,13 +127,21 @@ + HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, mask_sh),\ + HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh) + ++/*DCN2.x and DCN1.x*/ ++#define HUBP_MASK_SH_LIST_DCN2_COMMON(mask_sh)\ ++ HUBP_MASK_SH_LIST_DCN2_SHARE_COMMON(mask_sh),\ ++ HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\ ++ HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\ ++ HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh) ++ ++/*DCN2.0 specific*/ + #define HUBP_MASK_SH_LIST_DCN20(mask_sh)\ + HUBP_MASK_SH_LIST_DCN2_COMMON(mask_sh),\ + HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\ + HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\ + HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh) + +- ++/*DCN2.x */ + #define DCN2_HUBP_REG_COMMON_VARIABLE_LIST \ + HUBP_COMMON_REG_VARIABLE_LIST; \ + uint32_t DMDATA_ADDRESS_HIGH; \ +@@ -149,14 +157,11 @@ + uint32_t FLIP_PARAMETERS_2;\ + uint32_t DCN_CUR1_TTU_CNTL0;\ + uint32_t DCN_CUR1_TTU_CNTL1;\ +- uint32_t VMID_SETTINGS_0;\ +- uint32_t FLIP_PARAMETERS_3;\ +- uint32_t FLIP_PARAMETERS_4;\ +- uint32_t VBLANK_PARAMETERS_5;\ +- uint32_t VBLANK_PARAMETERS_6 ++ uint32_t VMID_SETTINGS_0 ++ + + #define DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type) \ +- DCN_HUBP_REG_FIELD_LIST(type); \ ++ DCN_HUBP_REG_FIELD_BASE_LIST(type); \ + type DMDATA_ADDRESS_HIGH;\ + type DMDATA_MODE;\ + type DMDATA_UPDATED;\ +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +index 8d3bc156de6f..f820e9667e3c 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +@@ -115,7 +115,7 @@ static void enable_power_gating_plane( + REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on); + } + +-static void dcn20_dccg_init(struct dce_hwseq *hws) ++void dcn20_dccg_init(struct dce_hwseq *hws) + { + /* + * set MICROSECOND_TIME_BASE_DIV +@@ -138,6 +138,45 @@ static void dcn20_dccg_init(struct dce_hwseq *hws) + /* This value is dependent on the hardware pipeline delay so set once per SOC */ + REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x801003c); + } ++void dcn20_display_init(struct dc *dc) ++{ ++ struct dce_hwseq *hws = dc->hwseq; ++ ++ /* RBBMIF ++ * disable RBBMIF timeout detection for all clients ++ * Ensure RBBMIF does not drop register accesses due to the per-client timeout ++ */ ++ REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF); ++ REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF); ++ ++ /* DCCG */ ++ dcn20_dccg_init(hws); ++ ++ /* Disable all memory low power mode. All memories are enabled. */ ++ REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, 1); ++ ++ /* DCHUB/MMHUBBUB ++ * set global timer refclk divider ++ * 100Mhz refclk -> 2 ++ * 27Mhz refclk -> 1 ++ * 48Mhz refclk -> 1 ++ */ ++ REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2); ++ REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); ++ REG_WRITE(REFCLK_CNTL, 0); ++ ++ /* OPTC ++ * OTG_CONTROL.OTG_DISABLE_POINT_CNTL = 0x3; will be set during optc2_enable_crtc ++ */ ++ ++ /* AZ ++ * default value is 0x64 for 100Mhz ref clock, if the ref clock is 100Mhz, no need to program this regiser, ++ * if not, it should be programmed according to the ref clock ++ */ ++ REG_UPDATE(AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, 0x64); ++ /* Enable controller clock gating */ ++ REG_WRITE(AZALIA_CONTROLLER_CLOCK_GATING, 0x1); ++} + + static void disable_vga( + struct dce_hwseq *hws) +@@ -163,7 +202,7 @@ void dcn20_program_tripleBuffer( + } + + /* Blank pixel data during initialization */ +-static void dcn20_init_blank( ++void dcn20_init_blank( + struct dc *dc, + struct timing_generator *tg) + { +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h +index 2b0409454073..689c2765b071 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h +@@ -91,13 +91,9 @@ void dcn20_pipe_control_lock_global( + void dcn20_setup_gsl_group_as_lock(const struct dc *dc, + struct pipe_ctx *pipe_ctx, + bool enable); +-void dcn20_pipe_control_lock( +- struct dc *dc, +- struct pipe_ctx *pipe, +- bool lock); +-void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx); +-void dcn20_enable_plane( +- struct dc *dc, +- struct pipe_ctx *pipe_ctx, +- struct dc_state *context); ++void dcn20_dccg_init(struct dce_hwseq *hws); ++void dcn20_init_blank( ++ struct dc *dc, ++ struct timing_generator *tg); ++void dcn20_display_init(struct dc *dc); + #endif /* __DC_HWSS_DCN20_H__ */ +-- +2.17.1 + |