diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2970-drm-amdgpu-add-arct-gc-golden-settings.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2970-drm-amdgpu-add-arct-gc-golden-settings.patch | 70 |
1 files changed, 70 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2970-drm-amdgpu-add-arct-gc-golden-settings.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2970-drm-amdgpu-add-arct-gc-golden-settings.patch new file mode 100644 index 00000000..43fb5aae --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2970-drm-amdgpu-add-arct-gc-golden-settings.patch @@ -0,0 +1,70 @@ +From c1e1981b537e0f907c144f484f19c83b3f23f150 Mon Sep 17 00:00:00 2001 +From: Hawking Zhang <Hawking.Zhang@amd.com> +Date: Thu, 27 Jun 2019 15:08:48 +0800 +Subject: [PATCH 2970/4256] drm/amdgpu: add arct gc golden settings + +Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> +Reviewed-by: Le Ma <Le.Ma@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 30 +++++++++++++++++++++++++++ + 1 file changed, 30 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +index a202ad5c329d..e85f3f8d4b45 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +@@ -107,6 +107,19 @@ MODULE_FIRMWARE("amdgpu/arcturus_mec.bin"); + MODULE_FIRMWARE("amdgpu/arcturus_mec2.bin"); + MODULE_FIRMWARE("amdgpu/arcturus_rlc.bin"); + ++#define mmTCP_CHAN_STEER_0_ARCT 0x0b03 ++#define mmTCP_CHAN_STEER_0_ARCT_BASE_IDX 0 ++#define mmTCP_CHAN_STEER_1_ARCT 0x0b04 ++#define mmTCP_CHAN_STEER_1_ARCT_BASE_IDX 0 ++#define mmTCP_CHAN_STEER_2_ARCT 0x0b09 ++#define mmTCP_CHAN_STEER_2_ARCT_BASE_IDX 0 ++#define mmTCP_CHAN_STEER_3_ARCT 0x0b0a ++#define mmTCP_CHAN_STEER_3_ARCT_BASE_IDX 0 ++#define mmTCP_CHAN_STEER_4_ARCT 0x0b0b ++#define mmTCP_CHAN_STEER_4_ARCT_BASE_IDX 0 ++#define mmTCP_CHAN_STEER_5_ARCT 0x0b0c ++#define mmTCP_CHAN_STEER_5_ARCT_BASE_IDX 0 ++ + static const struct soc15_reg_golden golden_settings_gc_9_0[] = + { + SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400), +@@ -274,6 +287,18 @@ static const struct soc15_reg_golden golden_settings_gc_9_2_1_vg12[] = + SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00000000, 0x00008000) + }; + ++static const struct soc15_reg_golden golden_settings_gc_9_4_1_arct[] = ++{ ++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042), ++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x10b0000), ++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_0_ARCT, 0x3fffffff, 0x346f0a4e), ++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_1_ARCT, 0x3fffffff, 0x1c642ca), ++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_2_ARCT, 0x3fffffff, 0x26f45098), ++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_3_ARCT, 0x3fffffff, 0x2ebd9fe3), ++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_4_ARCT, 0x3fffffff, 0xb90f5b1), ++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_5_ARCT, 0x3ff, 0x135), ++}; ++ + static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] = + { + mmRLC_SRM_INDEX_CNTL_ADDR_0 - mmRLC_SRM_INDEX_CNTL_ADDR_0, +@@ -343,6 +368,11 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev) + golden_settings_gc_9_0_vg20, + ARRAY_SIZE(golden_settings_gc_9_0_vg20)); + break; ++ case CHIP_ARCTURUS: ++ soc15_program_register_sequence(adev, ++ golden_settings_gc_9_4_1_arct, ++ ARRAY_SIZE(golden_settings_gc_9_4_1_arct)); ++ break; + case CHIP_RAVEN: + soc15_program_register_sequence(adev, golden_settings_gc_9_1, + ARRAY_SIZE(golden_settings_gc_9_1)); +-- +2.17.1 + |