diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2969-drm-amdgpu-add-arct-sdma-golden-settings.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2969-drm-amdgpu-add-arct-sdma-golden-settings.patch | 85 |
1 files changed, 85 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2969-drm-amdgpu-add-arct-sdma-golden-settings.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2969-drm-amdgpu-add-arct-sdma-golden-settings.patch new file mode 100644 index 00000000..1103376f --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2969-drm-amdgpu-add-arct-sdma-golden-settings.patch @@ -0,0 +1,85 @@ +From 4d6721ca1d47d0a098f383698088d1c716cb256b Mon Sep 17 00:00:00 2001 +From: Hawking Zhang <Hawking.Zhang@amd.com> +Date: Thu, 27 Jun 2019 14:47:42 +0800 +Subject: [PATCH 2969/4256] drm/amdgpu: add arct sdma golden settings + +Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> +Reviewed-by: Le Ma <Le.Ma@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 45 ++++++++++++++++++++++++++ + 1 file changed, 45 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +index 2660baa5ca32..48d4597ef9f6 100644 +--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +@@ -31,6 +31,18 @@ + #include "sdma0/sdma0_4_2_sh_mask.h" + #include "sdma1/sdma1_4_2_offset.h" + #include "sdma1/sdma1_4_2_sh_mask.h" ++#include "sdma2/sdma2_4_2_2_offset.h" ++#include "sdma2/sdma2_4_2_2_sh_mask.h" ++#include "sdma3/sdma3_4_2_2_offset.h" ++#include "sdma3/sdma3_4_2_2_sh_mask.h" ++#include "sdma4/sdma4_4_2_2_offset.h" ++#include "sdma4/sdma4_4_2_2_sh_mask.h" ++#include "sdma5/sdma5_4_2_2_offset.h" ++#include "sdma5/sdma5_4_2_2_sh_mask.h" ++#include "sdma6/sdma6_4_2_2_offset.h" ++#include "sdma6/sdma6_4_2_2_sh_mask.h" ++#include "sdma7/sdma7_4_2_2_offset.h" ++#include "sdma7/sdma7_4_2_2_sh_mask.h" + #include "hdp/hdp_4_0_offset.h" + #include "sdma0/sdma0_4_1_default.h" + +@@ -207,6 +219,34 @@ static const struct soc15_reg_golden golden_settings_sdma_rv2[] = + SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003001) + }; + ++static const struct soc15_reg_golden golden_settings_sdma_arct[] = ++{ ++ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), ++ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), ++ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), ++ SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07), ++ SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), ++ SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), ++ SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_CHICKEN_BITS, 0xfe931f07, 0x02831f07), ++ SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), ++ SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), ++ SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_CHICKEN_BITS, 0xfe931f07, 0x02831f07), ++ SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), ++ SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), ++ SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_CHICKEN_BITS, 0xfe931f07, 0x02831f07), ++ SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), ++ SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), ++ SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_CHICKEN_BITS, 0xfe931f07, 0x02831f07), ++ SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), ++ SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), ++ SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_CHICKEN_BITS, 0xfe931f07, 0x02831f07), ++ SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), ++ SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), ++ SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_CHICKEN_BITS, 0xfe931f07, 0x02831f07), ++ SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), ++ SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002) ++}; ++ + static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev, + u32 instance, u32 offset) + { +@@ -315,6 +355,11 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) + golden_settings_sdma1_4_2, + ARRAY_SIZE(golden_settings_sdma1_4_2)); + break; ++ case CHIP_ARCTURUS: ++ soc15_program_register_sequence(adev, ++ golden_settings_sdma_arct, ++ ARRAY_SIZE(golden_settings_sdma_arct)); ++ break; + case CHIP_RAVEN: + soc15_program_register_sequence(adev, + golden_settings_sdma_4_1, +-- +2.17.1 + |