diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1018-drm-amd-display-Rename-dc-validate_context-and-curre.patch')
-rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1018-drm-amd-display-Rename-dc-validate_context-and-curre.patch | 2169 |
1 files changed, 2169 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1018-drm-amd-display-Rename-dc-validate_context-and-curre.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1018-drm-amd-display-Rename-dc-validate_context-and-curre.patch new file mode 100644 index 00000000..1824ba26 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1018-drm-amd-display-Rename-dc-validate_context-and-curre.patch @@ -0,0 +1,2169 @@ +From 7e0d85e6596c914b9458c3e12dc6dc0fb68ec716 Mon Sep 17 00:00:00 2001 +From: Jerry Zuo <Jerry.Zuo@amd.com> +Date: Fri, 25 Aug 2017 16:16:10 -0400 +Subject: [PATCH 1018/4131] drm/amd/display: Rename dc validate_context and + current_context +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Rename all the dc validate_context to dc_stateĀ and +dc current_context to current_state. + +Change-Id: I39f896ac7f311f74ca26b78b822f12a9e2ff8583 +Signed-off-by: Jerry Zuo <Jerry.Zuo@amd.com> +Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> +--- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 +- + drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 6 +- + drivers/gpu/drm/amd/display/dc/core/dc.c | 106 ++++++++++----------- + drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 2 +- + drivers/gpu/drm/amd/display/dc/core/dc_link.c | 8 +- + drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +- + drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 4 +- + drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 40 ++++---- + drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 15 ++- + drivers/gpu/drm/amd/display/dc/core/dc_surface.c | 4 +- + drivers/gpu/drm/amd/display/dc/dc.h | 36 +++---- + .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 4 +- + .../amd/display/dc/dce100/dce100_hw_sequencer.c | 8 +- + .../amd/display/dc/dce100/dce100_hw_sequencer.h | 4 +- + .../drm/amd/display/dc/dce100/dce100_resource.c | 10 +- + .../amd/display/dc/dce110/dce110_hw_sequencer.c | 70 +++++++------- + .../amd/display/dc/dce110/dce110_hw_sequencer.h | 12 +-- + .../drm/amd/display/dc/dce110/dce110_resource.c | 16 ++-- + .../drm/amd/display/dc/dce112/dce112_resource.c | 16 ++-- + .../drm/amd/display/dc/dce112/dce112_resource.h | 10 +- + .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 10 +- + .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 62 ++++++------ + .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h | 2 +- + .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 8 +- + drivers/gpu/drm/amd/display/dc/inc/core_types.h | 14 +-- + drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h | 2 +- + drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h | 4 +- + drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 14 +-- + drivers/gpu/drm/amd/display/dc/inc/resource.h | 22 ++--- + .../amd/display/dc/irq/dce110/irq_service_dce110.c | 2 +- + .../gpu/drm/amd/display/include/logger_interface.h | 4 +- + 32 files changed, 262 insertions(+), 263 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +index cc34bfc..2ec21fe 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -820,7 +820,7 @@ struct drm_atomic_state * + dm_atomic_state_alloc(struct drm_device *dev) + { + struct dm_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL); +- struct validate_context *new_ctx; ++ struct dc_state *new_ctx; + struct amdgpu_device *adev = dev->dev_private; + struct dc *dc = adev->dm.dc; + +@@ -855,7 +855,7 @@ dm_atomic_state_clear(struct drm_atomic_state *state) + struct dm_atomic_state *dm_state = to_dm_atomic_state(state); + + if (dm_state->context) { +- dc_release_validate_context(dm_state->context); ++ dc_release_state(dm_state->context); + dm_state->context = NULL; + } + +@@ -4342,7 +4342,7 @@ void amdgpu_dm_atomic_commit_tail( + } + + if (dm_state->context) +- WARN_ON(!dc_commit_context(dm->dc, dm_state->context)); ++ WARN_ON(!dc_commit_state(dm->dc, dm_state->context)); + + + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +index 54acbb5..606bfbc 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +@@ -205,7 +205,7 @@ struct dm_crtc_state { + struct dm_atomic_state { + struct drm_atomic_state base; + +- struct validate_context *context; ++ struct dc_state *context; + }; + + #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) +diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +index 6c85a54..ee1b76c 100644 +--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c ++++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +@@ -476,7 +476,7 @@ static void dcn_bw_calc_rq_dlg_ttu( + static void dcn_dml_wm_override( + const struct dcn_bw_internal_vars *v, + struct display_mode_lib *dml, +- struct validate_context *context, ++ struct dc_state *context, + const struct resource_pool *pool) + { + int i, in_idx, active_count; +@@ -593,7 +593,7 @@ static void split_stream_across_pipes( + } + + static void calc_wm_sets_and_perf_params( +- struct validate_context *context, ++ struct dc_state *context, + struct dcn_bw_internal_vars *v) + { + /* Calculate set A last to keep internal var state consistent for required config */ +@@ -721,7 +721,7 @@ static bool dcn_bw_apply_registry_override(struct dc *dc) + + bool dcn_validate_bandwidth( + struct dc *dc, +- struct validate_context *context) ++ struct dc_state *context) + { + const struct resource_pool *pool = dc->res_pool; + struct dcn_bw_internal_vars *v = &context->dcn_bw_vars; +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c +index 5e56361..c032f9f 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c +@@ -160,7 +160,7 @@ static bool stream_adjust_vmin_vmax(struct dc *dc, + bool ret = false; + + for (i = 0; i < MAX_PIPES; i++) { +- struct pipe_ctx *pipe = &dc->current_context->res_ctx.pipe_ctx[i]; ++ struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; + + if (pipe->stream == stream && pipe->stream_res.stream_enc) { + dc->hwss.set_drr(&pipe, 1, vmin, vmax); +@@ -187,7 +187,7 @@ static bool stream_get_crtc_position(struct dc *dc, + + for (i = 0; i < MAX_PIPES; i++) { + struct pipe_ctx *pipe = +- &dc->current_context->res_ctx.pipe_ctx[i]; ++ &dc->current_state->res_ctx.pipe_ctx[i]; + + if (pipe->stream == stream && pipe->stream_res.stream_enc) { + dc->hwss.get_position(&pipe, 1, &position); +@@ -207,8 +207,8 @@ static bool set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream) + struct pipe_ctx *pipes; + + for (i = 0; i < MAX_PIPES; i++) { +- if (dc->current_context->res_ctx.pipe_ctx[i].stream == stream) { +- pipes = &dc->current_context->res_ctx.pipe_ctx[i]; ++ if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) { ++ pipes = &dc->current_state->res_ctx.pipe_ctx[i]; + dc->hwss.program_gamut_remap(pipes); + ret = true; + } +@@ -224,10 +224,10 @@ static bool program_csc_matrix(struct dc *dc, struct dc_stream_state *stream) + struct pipe_ctx *pipes; + + for (i = 0; i < MAX_PIPES; i++) { +- if (dc->current_context->res_ctx.pipe_ctx[i].stream ++ if (dc->current_state->res_ctx.pipe_ctx[i].stream + == stream) { + +- pipes = &dc->current_context->res_ctx.pipe_ctx[i]; ++ pipes = &dc->current_state->res_ctx.pipe_ctx[i]; + dc->hwss.program_csc_matrix(pipes, + stream->output_color_space, + stream->csc_color_matrix.matrix); +@@ -252,10 +252,10 @@ static void set_static_screen_events(struct dc *dc, + struct dc_stream_state *stream = streams[i]; + + for (j = 0; j < MAX_PIPES; j++) { +- if (dc->current_context->res_ctx.pipe_ctx[j].stream ++ if (dc->current_state->res_ctx.pipe_ctx[j].stream + == stream) { + pipes_affected[num_pipes_affected++] = +- &dc->current_context->res_ctx.pipe_ctx[j]; ++ &dc->current_state->res_ctx.pipe_ctx[j]; + } + } + } +@@ -334,7 +334,7 @@ void set_dither_option(struct dc_stream_state *stream, + { + struct bit_depth_reduction_params params; + struct dc_link *link = stream->status.link; +- struct pipe_ctx *pipes = link->dc->current_context->res_ctx.pipe_ctx; ++ struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx; + + memset(¶ms, 0, sizeof(params)); + if (!stream) +@@ -408,8 +408,8 @@ static void allocate_dc_stream_funcs(struct dc *dc) + + static void destruct(struct dc *dc) + { +- dc_release_validate_context(dc->current_context); +- dc->current_context = NULL; ++ dc_release_state(dc->current_state); ++ dc->current_state = NULL; + + destroy_links(dc); + +@@ -494,14 +494,14 @@ static bool construct(struct dc *dc, + goto fail; + } + +- dc->current_context = dm_alloc(sizeof(*dc->current_context)); ++ dc->current_state = dm_alloc(sizeof(*dc->current_state)); + +- if (!dc->current_context) { ++ if (!dc->current_state) { + dm_error("%s: failed to create validate ctx\n", __func__); + goto fail; + } + +- atomic_inc(&dc->current_context->ref_count); ++ atomic_inc(&dc->current_state->ref_count); + + dc_ctx->cgs_device = init_params->cgs_device; + dc_ctx->driver_context = init_params->driver; +@@ -670,12 +670,12 @@ bool dc_validate_guaranteed( + struct dc_stream_state *stream) + { + enum dc_status result = DC_ERROR_UNEXPECTED; +- struct validate_context *context; ++ struct dc_state *context; + + if (!dc_validate_stream(dc, stream)) + return false; + +- context = dm_alloc(sizeof(struct validate_context)); ++ context = dm_alloc(sizeof(struct dc_state)); + if (context == NULL) + goto context_alloc_fail; + +@@ -684,7 +684,7 @@ bool dc_validate_guaranteed( + result = dc->res_pool->funcs->validate_guaranteed( + dc, stream, context); + +- dc_release_validate_context(context); ++ dc_release_state(context); + + context_alloc_fail: + if (result != DC_OK) { +@@ -699,7 +699,7 @@ bool dc_validate_guaranteed( + + static void program_timing_sync( + struct dc *dc, +- struct validate_context *ctx) ++ struct dc_state *ctx) + { + int i, j; + int group_index = 0; +@@ -773,15 +773,15 @@ static void program_timing_sync( + + static bool context_changed( + struct dc *dc, +- struct validate_context *context) ++ struct dc_state *context) + { + uint8_t i; + +- if (context->stream_count != dc->current_context->stream_count) ++ if (context->stream_count != dc->current_state->stream_count) + return true; + +- for (i = 0; i < dc->current_context->stream_count; i++) { +- if (dc->current_context->streams[i] != context->streams[i]) ++ for (i = 0; i < dc->current_state->stream_count; i++) { ++ if (dc->current_state->streams[i] != context->streams[i]) + return true; + } + +@@ -790,7 +790,7 @@ static bool context_changed( + + bool dc_enable_stereo( + struct dc *dc, +- struct validate_context *context, ++ struct dc_state *context, + struct dc_stream_state *streams[], + uint8_t stream_count) + { +@@ -802,7 +802,7 @@ bool dc_enable_stereo( + if (context != NULL) + pipe = &context->res_ctx.pipe_ctx[i]; + else +- pipe = &dc->current_context->res_ctx.pipe_ctx[i]; ++ pipe = &dc->current_state->res_ctx.pipe_ctx[i]; + for (j = 0 ; pipe && j < stream_count; j++) { + if (streams[j] && streams[j] == pipe->stream && + dc->hwss.setup_stereo) +@@ -818,7 +818,7 @@ bool dc_enable_stereo( + * Applies given context to HW and copy it into current context. + * It's up to the user to release the src context afterwards. + */ +-static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *context) ++static bool dc_commit_state_no_check(struct dc *dc, struct dc_state *context) + { + struct dc_bios *dcb = dc->ctx->dc_bios; + enum dc_status result = DC_ERROR_UNEXPECTED; +@@ -877,18 +877,18 @@ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *c + + dc_enable_stereo(dc, context, dc_streams, context->stream_count); + +- dc_release_validate_context(dc->current_context); ++ dc_release_state(dc->current_state); + +- dc->current_context = context; ++ dc->current_state = context; + +- dc_retain_validate_context(dc->current_context); ++ dc_retain_state(dc->current_state); + + dc->hwss.optimize_shared_resources(dc); + + return (result == DC_OK); + } + +-bool dc_commit_context(struct dc *dc, struct validate_context *context) ++bool dc_commit_state(struct dc *dc, struct dc_state *context) + { + enum dc_status result = DC_ERROR_UNEXPECTED; + int i; +@@ -907,7 +907,7 @@ bool dc_commit_context(struct dc *dc, struct validate_context *context) + LOG_DC); + } + +- result = dc_commit_context_no_check(dc, context); ++ result = dc_commit_state_no_check(dc, context); + + return (result == DC_OK); + } +@@ -916,7 +916,7 @@ bool dc_commit_context(struct dc *dc, struct validate_context *context) + bool dc_post_update_surfaces_to_stream(struct dc *dc) + { + int i; +- struct validate_context *context = dc->current_context; ++ struct dc_state *context = dc->current_state; + + post_surface_trace(dc); + +@@ -1001,13 +1001,13 @@ bool dc_commit_planes_to_stream( + return true; + } + +-void dc_retain_validate_context(struct validate_context *context) ++void dc_retain_state(struct dc_state *context) + { + ASSERT(atomic_read(&context->ref_count) > 0); + atomic_inc(&context->ref_count); + } + +-void dc_release_validate_context(struct validate_context *context) ++void dc_release_state(struct dc_state *context) + { + ASSERT(atomic_read(&context->ref_count) > 0); + atomic_dec(&context->ref_count); +@@ -1019,7 +1019,7 @@ void dc_release_validate_context(struct validate_context *context) + } + + static bool is_surface_in_context( +- const struct validate_context *context, ++ const struct dc_state *context, + const struct dc_plane_state *plane_state) + { + int j; +@@ -1136,7 +1136,7 @@ static enum surface_update_type det_surface_update( + const struct dc_surface_update *u, + int surface_index) + { +- const struct validate_context *context = dc->current_context; ++ const struct dc_state *context = dc->current_state; + enum surface_update_type type = UPDATE_TYPE_FAST; + enum surface_update_type overall_type = UPDATE_TYPE_FAST; + +@@ -1191,7 +1191,7 @@ enum surface_update_type dc_check_update_surfaces_for_stream( + } + + static struct dc_stream_status *stream_get_status( +- struct validate_context *ctx, ++ struct dc_state *ctx, + struct dc_stream_state *stream) + { + uint8_t i; +@@ -1212,7 +1212,7 @@ void dc_update_planes_and_stream(struct dc *dc, + struct dc_stream_state *stream, + struct dc_stream_update *stream_update) + { +- struct validate_context *context; ++ struct dc_state *context; + int i, j; + enum surface_update_type update_type; + const struct dc_stream_status *stream_status; +@@ -1230,7 +1230,7 @@ void dc_update_planes_and_stream(struct dc *dc, + ASSERT(0); + } + #endif +- context = dc->current_context; ++ context = dc->current_state; + + /* update current stream with the new updates */ + if (stream_update) { +@@ -1286,7 +1286,7 @@ void dc_update_planes_and_stream(struct dc *dc, + atomic_inc(&context->ref_count); + + dc_resource_validate_ctx_copy_construct( +- dc->current_context, context); ++ dc->current_state, context); + + /*remove old surfaces from context */ + if (!dc_rem_all_planes_for_stream(dc, stream, context)) { +@@ -1430,7 +1430,7 @@ void dc_update_planes_and_stream(struct dc *dc, + /* Full fe update*/ + for (j = 0; j < dc->res_pool->pipe_count; j++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; +- struct pipe_ctx *cur_pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[j]; ++ struct pipe_ctx *cur_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[j]; + bool is_new_pipe_surface = cur_pipe_ctx->plane_state != pipe_ctx->plane_state; + struct dc_cursor_position position = { 0 }; + +@@ -1517,7 +1517,7 @@ void dc_update_planes_and_stream(struct dc *dc, + } + } + +- if (dc->current_context != context) { ++ if (dc->current_state != context) { + + /* Since memory free requires elevated IRQL, an interrupt + * request is generated by mem free. If this happens +@@ -1527,16 +1527,16 @@ void dc_update_planes_and_stream(struct dc *dc, + * then free the old context. + */ + +- struct validate_context *old = dc->current_context; ++ struct dc_state *old = dc->current_state; + +- dc->current_context = context; +- dc_release_validate_context(old); ++ dc->current_state = context; ++ dc_release_state(old); + + } + return; + + fail: +- dc_release_validate_context(context); ++ dc_release_state(context); + + context_alloc_fail: + DC_ERROR("Failed to allocate new validate context!\n"); +@@ -1544,13 +1544,13 @@ void dc_update_planes_and_stream(struct dc *dc, + + uint8_t dc_get_current_stream_count(struct dc *dc) + { +- return dc->current_context->stream_count; ++ return dc->current_state->stream_count; + } + + struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i) + { +- if (i < dc->current_context->stream_count) +- return dc->current_context->streams[i]; ++ if (i < dc->current_state->stream_count) ++ return dc->current_state->streams[i]; + return NULL; + } + +@@ -1659,11 +1659,11 @@ void dc_set_power_state( + */ + + /* Preserve refcount */ +- ref_count = dc->current_context->ref_count; +- dc_resource_validate_ctx_destruct(dc->current_context); +- memset(dc->current_context, 0, +- sizeof(*dc->current_context)); +- dc->current_context->ref_count = ref_count; ++ ref_count = dc->current_state->ref_count; ++ dc_resource_validate_ctx_destruct(dc->current_state); ++ memset(dc->current_state, 0, ++ sizeof(*dc->current_state)); ++ dc->current_state->ref_count = ref_count; + + break; + } +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +index d74eed8..6acee54 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +@@ -329,7 +329,7 @@ void context_timing_trace( + + void context_clock_trace( + struct dc *dc, +- struct validate_context *context) ++ struct dc_state *context) + { + #if defined(CONFIG_DRM_AMD_DC_DCN1_0) + struct dc *core_dc = dc; +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c +index 0bdd41c..65e1261 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c +@@ -1819,14 +1819,14 @@ bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level, + if (dc_is_embedded_signal(link->connector_signal)) { + if (stream != NULL) { + for (i = 0; i < MAX_PIPES; i++) { +- if (core_dc->current_context->res_ctx. ++ if (core_dc->current_state->res_ctx. + pipe_ctx[i].stream + == stream) + /* DMCU -1 for all controller id values, + * therefore +1 here + */ + controller_id = +- core_dc->current_context-> ++ core_dc->current_state-> + res_ctx.pipe_ctx[i].stream_res.tg->inst + + 1; + } +@@ -1926,13 +1926,13 @@ bool dc_link_setup_psr(struct dc_link *link, + psr_context->engineId = link->link_enc->preferred_engine; + + for (i = 0; i < MAX_PIPES; i++) { +- if (core_dc->current_context->res_ctx.pipe_ctx[i].stream ++ if (core_dc->current_state->res_ctx.pipe_ctx[i].stream + == stream) { + /* dmcu -1 for all controller id values, + * therefore +1 here + */ + psr_context->controllerId = +- core_dc->current_context->res_ctx. ++ core_dc->current_state->res_ctx. + pipe_ctx[i].stream_res.tg->inst + 1; + break; + } +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +index 446e293..5f2b52e 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +@@ -2406,7 +2406,7 @@ bool dc_link_dp_set_test_pattern( + const unsigned char *p_custom_pattern, + unsigned int cust_pattern_size) + { +- struct pipe_ctx *pipes = link->dc->current_context->res_ctx.pipe_ctx; ++ struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx; + struct pipe_ctx *pipe_ctx = &pipes[0]; + unsigned int lane; + unsigned int i; +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c +index 23d8b61..3427fb5 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c +@@ -62,7 +62,7 @@ void dp_enable_link_phy( + struct link_encoder *link_enc = link->link_enc; + + struct pipe_ctx *pipes = +- link->dc->current_context->res_ctx.pipe_ctx; ++ link->dc->current_state->res_ctx.pipe_ctx; + struct clock_source *dp_cs = + link->dc->res_pool->dp_clock_source; + unsigned int i; +@@ -262,7 +262,7 @@ void dp_retrain_link_dp_test(struct dc_link *link, + bool skip_video_pattern) + { + struct pipe_ctx *pipes = +- &link->dc->current_context->res_ctx.pipe_ctx[0]; ++ &link->dc->current_state->res_ctx.pipe_ctx[0]; + unsigned int i; + + for (i = 0; i < MAX_PIPES; i++) { +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +index 2ee3399..b5ccbdb 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +@@ -893,7 +893,7 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) + + enum dc_status resource_build_scaling_params_for_context( + const struct dc *dc, +- struct validate_context *context) ++ struct dc_state *context) + { + int i; + +@@ -971,7 +971,7 @@ static struct pipe_ctx *resource_get_tail_pipe_for_stream( + * that has no surface attached yet + */ + static struct pipe_ctx *acquire_free_pipe_for_stream( +- struct validate_context *context, ++ struct dc_state *context, + const struct resource_pool *pool, + struct dc_stream_state *stream) + { +@@ -1048,7 +1048,7 @@ bool dc_add_plane_to_context( + const struct dc *dc, + struct dc_stream_state *stream, + struct dc_plane_state *plane_state, +- struct validate_context *context) ++ struct dc_state *context) + { + int i; + struct resource_pool *pool = dc->res_pool; +@@ -1124,7 +1124,7 @@ bool dc_remove_plane_from_context( + const struct dc *dc, + struct dc_stream_state *stream, + struct dc_plane_state *plane_state, +- struct validate_context *context) ++ struct dc_state *context) + { + int i; + struct dc_stream_status *stream_status = NULL; +@@ -1199,7 +1199,7 @@ bool dc_remove_plane_from_context( + bool dc_rem_all_planes_for_stream( + const struct dc *dc, + struct dc_stream_state *stream, +- struct validate_context *context) ++ struct dc_state *context) + { + int i, old_plane_count; + struct dc_stream_status *stream_status = NULL; +@@ -1233,7 +1233,7 @@ static bool add_all_planes_for_stream( + struct dc_stream_state *stream, + const struct dc_validation_set set[], + int set_count, +- struct validate_context *context) ++ struct dc_state *context) + { + int i, j; + +@@ -1258,7 +1258,7 @@ bool dc_add_all_planes_for_stream( + struct dc_stream_state *stream, + struct dc_plane_state * const *plane_states, + int plane_count, +- struct validate_context *context) ++ struct dc_state *context) + { + struct dc_validation_set set; + int i; +@@ -1434,7 +1434,7 @@ static struct audio *find_first_free_audio( + } + + bool resource_is_stream_unchanged( +- struct validate_context *old_context, struct dc_stream_state *stream) ++ struct dc_state *old_context, struct dc_stream_state *stream) + { + int i; + +@@ -1450,7 +1450,7 @@ bool resource_is_stream_unchanged( + + bool dc_add_stream_to_ctx( + struct dc *dc, +- struct validate_context *new_ctx, ++ struct dc_state *new_ctx, + struct dc_stream_state *stream) + { + struct dc_context *dc_ctx = dc->ctx; +@@ -1474,7 +1474,7 @@ bool dc_add_stream_to_ctx( + + bool dc_remove_stream_from_ctx( + struct dc *dc, +- struct validate_context *new_ctx, ++ struct dc_state *new_ctx, + struct dc_stream_state *stream) + { + int i; +@@ -1553,7 +1553,7 @@ static void copy_pipe_ctx( + + static struct dc_stream_state *find_pll_sharable_stream( + struct dc_stream_state *stream_needs_pll, +- struct validate_context *context) ++ struct dc_state *context) + { + int i; + +@@ -1615,7 +1615,7 @@ static void calculate_phy_pix_clks(struct dc_stream_state *stream) + + enum dc_status resource_map_pool_resources( + const struct dc *dc, +- struct validate_context *context, ++ struct dc_state *context, + struct dc_stream_state *stream) + { + const struct resource_pool *pool = dc->res_pool; +@@ -1689,7 +1689,7 @@ enum dc_status resource_map_pool_resources( + + /* first stream in the context is used to populate the rest */ + void validate_guaranteed_copy_streams( +- struct validate_context *context, ++ struct dc_state *context, + int max_streams) + { + int i; +@@ -1709,14 +1709,14 @@ void validate_guaranteed_copy_streams( + + void dc_resource_validate_ctx_copy_construct_current( + const struct dc *dc, +- struct validate_context *dst_ctx) ++ struct dc_state *dst_ctx) + { +- dc_resource_validate_ctx_copy_construct(dc->current_context, dst_ctx); ++ dc_resource_validate_ctx_copy_construct(dc->current_state, dst_ctx); + } + + bool dc_validate_global_state( + struct dc *dc, +- struct validate_context *new_ctx) ++ struct dc_state *new_ctx) + { + enum dc_status result = DC_ERROR_UNEXPECTED; + int i, j; +@@ -2413,7 +2413,7 @@ static void set_vsc_info_packet( + /*TODO: stereo 3D support and extend pixel encoding colorimetry*/ + } + +-void dc_resource_validate_ctx_destruct(struct validate_context *context) ++void dc_resource_validate_ctx_destruct(struct dc_state *context) + { + int i, j; + +@@ -2433,8 +2433,8 @@ void dc_resource_validate_ctx_destruct(struct validate_context *context) + * by the src_ctx + */ + void dc_resource_validate_ctx_copy_construct( +- const struct validate_context *src_ctx, +- struct validate_context *dst_ctx) ++ const struct dc_state *src_ctx, ++ struct dc_state *dst_ctx) + { + int i, j; + atomic_t ref_count = dst_ctx->ref_count; +@@ -2518,7 +2518,7 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx) + + enum dc_status resource_map_clock_resources( + const struct dc *dc, +- struct validate_context *context, ++ struct dc_state *context, + struct dc_stream_state *stream) + { + /* acquire new resources */ +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +index 0e7cc29..a421779 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +@@ -169,10 +169,9 @@ struct dc_stream_status *dc_stream_get_status( + uint8_t i; + struct dc *dc = stream->ctx->dc; + +- for (i = 0; i < dc->current_context->stream_count; i++) { +- if (stream == dc->current_context->streams[i]) { +- return &dc->current_context->stream_status[i]; +- } ++ for (i = 0; i < dc->current_state->stream_count; i++) { ++ if (stream == dc->current_state->streams[i]) ++ return &dc->current_state->stream_status[i]; + } + + return NULL; +@@ -199,7 +198,7 @@ bool dc_stream_set_cursor_attributes( + } + + core_dc = stream->ctx->dc; +- res_ctx = &core_dc->current_context->res_ctx; ++ res_ctx = &core_dc->current_state->res_ctx; + + for (i = 0; i < MAX_PIPES; i++) { + struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; +@@ -235,7 +234,7 @@ bool dc_stream_set_cursor_position( + } + + core_dc = stream->ctx->dc; +- res_ctx = &core_dc->current_context->res_ctx; ++ res_ctx = &core_dc->current_state->res_ctx; + + for (i = 0; i < MAX_PIPES; i++) { + struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; +@@ -271,7 +270,7 @@ uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream) + uint8_t i; + struct dc *core_dc = stream->ctx->dc; + struct resource_context *res_ctx = +- &core_dc->current_context->res_ctx; ++ &core_dc->current_state->res_ctx; + + for (i = 0; i < MAX_PIPES; i++) { + struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; +@@ -295,7 +294,7 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, + bool ret = false; + struct dc *core_dc = stream->ctx->dc; + struct resource_context *res_ctx = +- &core_dc->current_context->res_ctx; ++ &core_dc->current_state->res_ctx; + + for (i = 0; i < MAX_PIPES; i++) { + struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c +index 0b6410f..e96f63e 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c +@@ -104,12 +104,12 @@ const struct dc_plane_status *dc_plane_get_status( + plane_status = &plane_state->status; + core_dc = plane_state->ctx->dc; + +- if (core_dc->current_context == NULL) ++ if (core_dc->current_state == NULL) + return NULL; + + for (i = 0; i < core_dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = +- &core_dc->current_context->res_ctx.pipe_ctx[i]; ++ &core_dc->current_state->res_ctx.pipe_ctx[i]; + + if (pipe_ctx->plane_state != plane_state) + continue; +diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h +index d01d54e..3cbff8c 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc.h ++++ b/drivers/gpu/drm/amd/display/dc/dc.h +@@ -99,7 +99,7 @@ struct dc_static_screen_events { + /* Forward declaration*/ + struct dc; + struct dc_plane_state; +-struct validate_context; ++struct dc_state; + + struct dc_cap_funcs { + bool (*get_dcc_compression_cap)(const struct dc *dc, +@@ -192,7 +192,7 @@ struct dc_debug { + bool disable_psr; + bool force_abm_enable; + }; +-struct validate_context; ++struct dc_state; + struct resource_pool; + struct dce_hwseq; + struct dc { +@@ -208,7 +208,7 @@ struct dc { + uint8_t link_count; + struct dc_link *links[MAX_PIPES * 2]; + +- struct validate_context *current_context; ++ struct dc_state *current_state; + struct resource_pool *res_pool; + + /*Power State*/ +@@ -637,12 +637,12 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, + + bool dc_add_stream_to_ctx( + struct dc *dc, +- struct validate_context *new_ctx, ++ struct dc_state *new_ctx, + struct dc_stream_state *stream); + + bool dc_remove_stream_from_ctx( + struct dc *dc, +- struct validate_context *new_ctx, ++ struct dc_state *new_ctx, + struct dc_stream_state *stream); + + +@@ -650,25 +650,25 @@ bool dc_add_plane_to_context( + const struct dc *dc, + struct dc_stream_state *stream, + struct dc_plane_state *plane_state, +- struct validate_context *context); ++ struct dc_state *context); + + bool dc_remove_plane_from_context( + const struct dc *dc, + struct dc_stream_state *stream, + struct dc_plane_state *plane_state, +- struct validate_context *context); ++ struct dc_state *context); + + bool dc_rem_all_planes_for_stream( + const struct dc *dc, + struct dc_stream_state *stream, +- struct validate_context *context); ++ struct dc_state *context); + + bool dc_add_all_planes_for_stream( + const struct dc *dc, + struct dc_stream_state *stream, + struct dc_plane_state * const *plane_states, + int plane_count, +- struct validate_context *context); ++ struct dc_state *context); + + /* + * Structure to store surface/stream associations for validation +@@ -685,7 +685,7 @@ bool dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); + + bool dc_validate_global_state( + struct dc *dc, +- struct validate_context *new_ctx); ++ struct dc_state *new_ctx); + + /* + * This function takes a stream and checks if it is guaranteed to be supported. +@@ -696,14 +696,14 @@ bool dc_validate_global_state( + */ + + void dc_resource_validate_ctx_copy_construct( +- const struct validate_context *src_ctx, +- struct validate_context *dst_ctx); ++ const struct dc_state *src_ctx, ++ struct dc_state *dst_ctx); + + void dc_resource_validate_ctx_copy_construct_current( + const struct dc *dc, +- struct validate_context *dst_ctx); ++ struct dc_state *dst_ctx); + +-void dc_resource_validate_ctx_destruct(struct validate_context *context); ++void dc_resource_validate_ctx_destruct(struct dc_state *context); + + /* + * TODO update to make it about validation sets +@@ -714,7 +714,7 @@ void dc_resource_validate_ctx_destruct(struct validate_context *context); + * Phy, Encoder, Timing Generator are programmed and enabled. + * New streams are enabled with blank stream; no memory read. + */ +-bool dc_commit_context(struct dc *dc, struct validate_context *context); ++bool dc_commit_state(struct dc *dc, struct dc_state *context); + + /* + * Set up streams and links associated to drive sinks +@@ -730,7 +730,7 @@ bool dc_commit_context(struct dc *dc, struct validate_context *context); + */ + bool dc_enable_stereo( + struct dc *dc, +- struct validate_context *context, ++ struct dc_state *context, + struct dc_stream_state *streams[], + uint8_t stream_count); + +@@ -753,8 +753,8 @@ enum surface_update_type dc_check_update_surfaces_for_stream( + const struct dc_stream_status *stream_status); + + +-void dc_retain_validate_context(struct validate_context *context); +-void dc_release_validate_context(struct validate_context *context); ++void dc_retain_state(struct dc_state *context); ++void dc_release_state(struct dc_state *context); + + /******************************************************************************* + * Link Interfaces +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +index 0654fe3..d3b61b9 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +@@ -609,7 +609,7 @@ static uint32_t dce110_get_pll_pixel_rate_in_hz( + { + uint32_t inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; + struct dc *dc_core = cs->ctx->dc; +- struct validate_context *context = dc_core->current_context; ++ struct dc_state *context = dc_core->current_state; + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[inst]; + + /* This function need separate to different DCE version, before separate, just use pixel clock */ +@@ -624,7 +624,7 @@ static uint32_t dce110_get_dp_pixel_rate_from_combo_phy_pll( + { + uint32_t inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; + struct dc *dc_core = cs->ctx->dc; +- struct validate_context *context = dc_core->current_context; ++ struct dc_state *context = dc_core->current_state; + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[inst]; + + /* This function need separate to different DCE version, before separate, just use pixel clock */ +diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c +index b7e51c5..492ea60 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c +@@ -107,7 +107,7 @@ static bool dce100_enable_display_power_gating( + + static void dce100_pplib_apply_display_requirements( + struct dc *dc, +- struct validate_context *context) ++ struct dc_state *context) + { + struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; + +@@ -127,14 +127,14 @@ static void dce100_pplib_apply_display_requirements( + + void dce100_set_bandwidth( + struct dc *dc, +- struct validate_context *context, ++ struct dc_state *context, + bool decrease_allowed) + { +- if (decrease_allowed || context->bw.dce.dispclk_khz > dc->current_context->bw.dce.dispclk_khz) { ++ if (decrease_allowed || context->bw.dce.dispclk_khz > dc->current_state->bw.dce.dispclk_khz) { + dc->res_pool->display_clock->funcs->set_clock( + dc->res_pool->display_clock, + context->bw.dce.dispclk_khz * 115 / 100); +- dc->current_context->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz; ++ dc->current_state->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz; + } + dce100_pplib_apply_display_requirements(dc, context); + } +diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h +index c04aa15..770b5bb 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h ++++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h +@@ -29,13 +29,13 @@ + #include "core_types.h" + + struct dc; +-struct validate_context; ++struct dc_state; + + bool dce100_hw_sequencer_construct(struct dc *dc); + + void dce100_set_bandwidth( + struct dc *dc, +- struct validate_context *context, ++ struct dc_state *context, + bool decrease_allowed); + + #endif /* __DC_HWSS_DCE100_H__ */ +diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +index c991610..36d7917 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +@@ -653,7 +653,7 @@ static void destruct(struct dce110_resource_pool *pool) + + static enum dc_status build_mapped_resource( + const struct dc *dc, +- struct validate_context *context, ++ struct dc_state *context, + struct dc_stream_state *stream) + { + enum dc_status status = DC_OK; +@@ -674,7 +674,7 @@ static enum dc_status build_mapped_resource( + + bool dce100_validate_bandwidth( + struct dc *dc, +- struct validate_context *context) ++ struct dc_state *context) + { + /* TODO implement when needed but for now hardcode max value*/ + context->bw.dce.dispclk_khz = 681000; +@@ -684,7 +684,7 @@ bool dce100_validate_bandwidth( + } + + static bool dce100_validate_surface_sets( +- struct validate_context *context) ++ struct dc_state *context) + { + int i; + +@@ -705,7 +705,7 @@ static bool dce100_validate_surface_sets( + + enum dc_status dce100_validate_global( + struct dc *dc, +- struct validate_context *context) ++ struct dc_state *context) + { + if (!dce100_validate_surface_sets(context)) + return DC_FAIL_SURFACE_VALIDATE; +@@ -716,7 +716,7 @@ enum dc_status dce100_validate_global( + enum dc_status dce100_validate_guaranteed( + struct dc *dc, + struct dc_stream_state *dc_stream, +- struct validate_context *context) ++ struct dc_state *context) + { + enum dc_status result = DC_ERROR_UNEXPECTED; + +diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +index 6ab585e..6e8c02d 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +@@ -976,11 +976,11 @@ static void program_scaler(const struct dc *dc, + + static enum dc_status dce110_prog_pixclk_crtc_otg( + struct pipe_ctx *pipe_ctx, +- struct validate_context *context, ++ struct dc_state *context, + struct dc *dc) + { + struct dc_stream_state *stream = pipe_ctx->stream; +- struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx. ++ struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx. + pipe_ctx[pipe_ctx->pipe_idx]; + struct tg_color black_color = {0}; + +@@ -1032,11 +1032,11 @@ static enum dc_status dce110_prog_pixclk_crtc_otg( + + static enum dc_status apply_single_controller_ctx_to_hw( + struct pipe_ctx *pipe_ctx, +- struct validate_context *context, ++ struct dc_state *context, + struct dc *dc) + { + struct dc_stream_state *stream = pipe_ctx->stream; +- struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx. ++ struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx. + pipe_ctx[pipe_ctx->pipe_idx]; + + /* */ +@@ -1252,7 +1252,7 @@ static uint32_t compute_pstate_blackout_duration( + + void dce110_set_displaymarks( + const struct dc *dc, +- struct validate_context *context) ++ struct dc_state *context) + { + uint8_t i, num_pipes; + unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; +@@ -1410,7 +1410,7 @@ static void set_static_screen_control(struct pipe_ctx **pipe_ctx, + */ + static uint32_t get_max_pixel_clock_for_all_paths( + struct dc *dc, +- struct validate_context *context, ++ struct dc_state *context, + bool pre_mode_set) + { + uint32_t max_pix_clk = 0; +@@ -1451,7 +1451,7 @@ static uint32_t get_max_pixel_clock_for_all_paths( + */ + static void apply_min_clocks( + struct dc *dc, +- struct validate_context *context, ++ struct dc_state *context, + enum dm_pp_clocks_state *clocks_state, + bool pre_mode_set) + { +@@ -1540,7 +1540,7 @@ static void apply_min_clocks( + * Check if FBC can be enabled + */ + static enum dc_status validate_fbc(struct dc *dc, +- struct validate_context *context) ++ struct dc_state *context) + { + struct pipe_ctx *pipe_ctx = + &context->res_ctx.pipe_ctx[0]; +@@ -1570,7 +1570,7 @@ static enum dc_status validate_fbc(struct dc *dc, + * Enable FBC + */ + static enum dc_status enable_fbc(struct dc *dc, +- struct validate_context *context) ++ struct dc_state *context) + { + enum dc_status status = validate_fbc(dc, context); + +@@ -1599,14 +1599,14 @@ static enum dc_status enable_fbc(struct dc *dc, + + static enum dc_status apply_ctx_to_hw_fpga( + struct dc *dc, +- struct validate_context *context) ++ struct dc_state *context) + { + enum dc_status status = DC_ERROR_UNEXPECTED; + int i; + + for (i = 0; i < MAX_PIPES; i++) { + struct pipe_ctx *pipe_ctx_old = +- &dc->current_context->res_ctx.pipe_ctx[i]; ++ &dc->current_state->res_ctx.pipe_ctx[i]; + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + + if (pipe_ctx->stream == NULL) +@@ -1629,7 +1629,7 @@ static enum dc_status apply_ctx_to_hw_fpga( + + static void dce110_reset_hw_ctx_wrap( + struct dc *dc, +- struct validate_context *context) ++ struct dc_state *context) + { + int i; + +@@ -1637,7 +1637,7 @@ static void dce110_reset_hw_ctx_wrap( + /* look up the targets that have been removed since last commit */ + for (i = 0; i < MAX_PIPES; i++) { + struct pipe_ctx *pipe_ctx_old = +- &dc->current_context->res_ctx.pipe_ctx[i]; ++ &dc->current_state->res_ctx.pipe_ctx[i]; + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + + /* Note: We need to disable output if clock sources change, +@@ -1659,9 +1659,9 @@ static void dce110_reset_hw_ctx_wrap( + } + pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg); + pipe_ctx_old->plane_res.mi->funcs->free_mem_input( +- pipe_ctx_old->plane_res.mi, dc->current_context->stream_count); ++ pipe_ctx_old->plane_res.mi, dc->current_state->stream_count); + resource_unreference_clock_source( +- &dc->current_context->res_ctx, dc->res_pool, ++ &dc->current_state->res_ctx, dc->res_pool, + &pipe_ctx_old->clock_source); + + dc->hwss.power_down_front_end(dc, pipe_ctx_old->pipe_idx); +@@ -1674,7 +1674,7 @@ static void dce110_reset_hw_ctx_wrap( + + enum dc_status dce110_apply_ctx_to_hw( + struct dc *dc, +- struct validate_context *context) ++ struct dc_state *context) + { + struct dc_bios *dcb = dc->ctx->dc_bios; + enum dc_status status; +@@ -1700,7 +1700,7 @@ enum dc_status dce110_apply_ctx_to_hw( + /* below is for real asic only */ + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx_old = +- &dc->current_context->res_ctx.pipe_ctx[i]; ++ &dc->current_state->res_ctx.pipe_ctx[i]; + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + + if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe) +@@ -1730,31 +1730,31 @@ enum dc_status dce110_apply_ctx_to_hw( + #if defined(CONFIG_DRM_AMD_DC_DCN1_0) + if (dc->ctx->dce_version >= DCN_VERSION_1_0) { + if (context->bw.dcn.calc_clk.fclk_khz +- > dc->current_context->bw.dcn.cur_clk.fclk_khz) { ++ > dc->current_state->bw.dcn.cur_clk.fclk_khz) { + struct dm_pp_clock_for_voltage_req clock; + + clock.clk_type = DM_PP_CLOCK_TYPE_FCLK; + clock.clocks_in_khz = context->bw.dcn.calc_clk.fclk_khz; + dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock); +- dc->current_context->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz; ++ dc->current_state->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz; + context->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz; + } + if (context->bw.dcn.calc_clk.dcfclk_khz +- > dc->current_context->bw.dcn.cur_clk.dcfclk_khz) { ++ > dc->current_state->bw.dcn.cur_clk.dcfclk_khz) { + struct dm_pp_clock_for_voltage_req clock; + + clock.clk_type = DM_PP_CLOCK_TYPE_DCFCLK; + clock.clocks_in_khz = context->bw.dcn.calc_clk.dcfclk_khz; + dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock); +- dc->current_context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz; ++ dc->current_state->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz; + context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz; + } + if (context->bw.dcn.calc_clk.dispclk_khz +- > dc->current_context->bw.dcn.cur_clk.dispclk_khz) { ++ > dc->current_state->bw.dcn.cur_clk.dispclk_khz) { + dc->res_pool->display_clock->funcs->set_clock( + dc->res_pool->display_clock, + context->bw.dcn.calc_clk.dispclk_khz); +- dc->current_context->bw.dcn.cur_clk.dispclk_khz = ++ dc->current_state->bw.dcn.cur_clk.dispclk_khz = + context->bw.dcn.calc_clk.dispclk_khz; + context->bw.dcn.cur_clk.dispclk_khz = + context->bw.dcn.calc_clk.dispclk_khz; +@@ -1762,7 +1762,7 @@ enum dc_status dce110_apply_ctx_to_hw( + } else + #endif + if (context->bw.dce.dispclk_khz +- > dc->current_context->bw.dce.dispclk_khz) { ++ > dc->current_state->bw.dce.dispclk_khz) { + dc->res_pool->display_clock->funcs->set_clock( + dc->res_pool->display_clock, + context->bw.dce.dispclk_khz * 115 / 100); +@@ -1843,7 +1843,7 @@ enum dc_status dce110_apply_ctx_to_hw( + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx_old = +- &dc->current_context->res_ctx.pipe_ctx[i]; ++ &dc->current_state->res_ctx.pipe_ctx[i]; + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + + if (pipe_ctx->stream == NULL) +@@ -2322,7 +2322,7 @@ static void init_hw(struct dc *dc) + } + + void dce110_fill_display_configs( +- const struct validate_context *context, ++ const struct dc_state *context, + struct dm_pp_display_configuration *pp_display_cfg) + { + int j; +@@ -2370,7 +2370,7 @@ void dce110_fill_display_configs( + pp_display_cfg->display_count = num_cfgs; + } + +-uint32_t dce110_get_min_vblank_time_us(const struct validate_context *context) ++uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context) + { + uint8_t j; + uint32_t min_vertical_blank_time = -1; +@@ -2422,7 +2422,7 @@ static int determine_sclk_from_bounding_box( + + static void pplib_apply_display_requirements( + struct dc *dc, +- struct validate_context *context) ++ struct dc_state *context) + { + struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; + +@@ -2476,16 +2476,16 @@ static void pplib_apply_display_requirements( + + static void dce110_set_bandwidth( + struct dc *dc, +- struct validate_context *context, ++ struct dc_state *context, + bool decrease_allowed) + { + dce110_set_displaymarks(dc, context); + +- if (decrease_allowed || context->bw.dce.dispclk_khz > dc->current_context->bw.dce.dispclk_khz) { ++ if (decrease_allowed || context->bw.dce.dispclk_khz > dc->current_state->bw.dce.dispclk_khz) { + dc->res_pool->display_clock->funcs->set_clock( + dc->res_pool->display_clock, + context->bw.dce.dispclk_khz * 115 / 100); +- dc->current_context->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz; ++ dc->current_state->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz; + } + + pplib_apply_display_requirements(dc, context); +@@ -2503,8 +2503,8 @@ static void dce110_program_front_end_for_pipe( + + memset(&tbl_entry, 0, sizeof(tbl_entry)); + +- if (dc->current_context) +- old_pipe = &dc->current_context->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; ++ if (dc->current_state) ++ old_pipe = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; + + memset(&adjust, 0, sizeof(adjust)); + adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; +@@ -2622,7 +2622,7 @@ static void dce110_apply_ctx_for_surface( + struct dc *dc, + const struct dc_stream_state *stream, + int num_planes, +- struct validate_context *context) ++ struct dc_state *context) + { + int i, be_idx; + +@@ -2652,7 +2652,7 @@ static void dce110_apply_ctx_for_surface( + static void dce110_power_down_fe(struct dc *dc, int fe_idx) + { + /* Do not power down fe when stream is active on dce*/ +- if (dc->current_context->res_ctx.pipe_ctx[fe_idx].stream) ++ if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream) + return; + + dc->hwss.enable_display_power_gating( +diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h +index ac418fd..baa20c1 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h ++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h +@@ -30,20 +30,20 @@ + + #define GAMMA_HW_POINTS_NUM 256 + struct dc; +-struct validate_context; ++struct dc_state; + struct dm_pp_display_configuration; + + bool dce110_hw_sequencer_construct(struct dc *dc); + + enum dc_status dce110_apply_ctx_to_hw( + struct dc *dc, +- struct validate_context *context); ++ struct dc_state *context); + +-void dce110_set_display_clock(struct validate_context *context); ++void dce110_set_display_clock(struct dc_state *context); + + void dce110_set_displaymarks( + const struct dc *dc, +- struct validate_context *context); ++ struct dc_state *context); + + void dce110_enable_stream(struct pipe_ctx *pipe_ctx); + +@@ -62,10 +62,10 @@ void dce110_power_down(struct dc *dc); + void dce110_update_pending_status(struct pipe_ctx *pipe_ctx); + + void dce110_fill_display_configs( +- const struct validate_context *context, ++ const struct dc_state *context, + struct dm_pp_display_configuration *pp_display_cfg); + +-uint32_t dce110_get_min_vblank_time_us(const struct validate_context *context); ++uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context); + + void dp_receiver_power_ctrl(struct dc_link *link, bool on); + #endif /* __DC_HWSS_DCE110_H__ */ +diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +index 18c67f8..94b6eb8 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +@@ -773,7 +773,7 @@ static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigne + + static enum dc_status build_mapped_resource( + const struct dc *dc, +- struct validate_context *context, ++ struct dc_state *context, + struct dc_stream_state *stream) + { + enum dc_status status = DC_OK; +@@ -800,7 +800,7 @@ static enum dc_status build_mapped_resource( + + static bool dce110_validate_bandwidth( + struct dc *dc, +- struct validate_context *context) ++ struct dc_state *context) + { + bool result = false; + +@@ -826,7 +826,7 @@ static bool dce110_validate_bandwidth( + context->streams[0]->timing.v_addressable, + context->streams[0]->timing.pix_clk_khz); + +- if (memcmp(&dc->current_context->bw.dce, ++ if (memcmp(&dc->current_state->bw.dce, + &context->bw.dce, sizeof(context->bw.dce))) { + struct log_entry log_entry; + dm_logger_open( +@@ -880,7 +880,7 @@ static bool dce110_validate_bandwidth( + } + + static bool dce110_validate_surface_sets( +- struct validate_context *context) ++ struct dc_state *context) + { + int i; + +@@ -913,7 +913,7 @@ static bool dce110_validate_surface_sets( + + enum dc_status dce110_validate_global( + struct dc *dc, +- struct validate_context *context) ++ struct dc_state *context) + { + if (!dce110_validate_surface_sets(context)) + return DC_FAIL_SURFACE_VALIDATE; +@@ -924,7 +924,7 @@ enum dc_status dce110_validate_global( + static enum dc_status dce110_validate_guaranteed( + struct dc *dc, + struct dc_stream_state *dc_stream, +- struct validate_context *context) ++ struct dc_state *context) + { + enum dc_status result = DC_ERROR_UNEXPECTED; + +@@ -954,7 +954,7 @@ static enum dc_status dce110_validate_guaranteed( + } + + static struct pipe_ctx *dce110_acquire_underlay( +- struct validate_context *context, ++ struct dc_state *context, + const struct resource_pool *pool, + struct dc_stream_state *stream) + { +@@ -976,7 +976,7 @@ static struct pipe_ctx *dce110_acquire_underlay( + + pipe_ctx->stream = stream; + +- if (!dc->current_context->res_ctx.pipe_ctx[underlay_idx].stream) { ++ if (!dc->current_state->res_ctx.pipe_ctx[underlay_idx].stream) { + struct tg_color black_color = {0}; + struct dc_bios *dcb = dc->ctx->dc_bios; + +diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +index d5a8ee6..de6f71d 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +@@ -724,7 +724,7 @@ static struct clock_source *find_matching_pll( + + static enum dc_status build_mapped_resource( + const struct dc *dc, +- struct validate_context *context, ++ struct dc_state *context, + struct dc_stream_state *stream) + { + enum dc_status status = DC_OK; +@@ -745,7 +745,7 @@ static enum dc_status build_mapped_resource( + + bool dce112_validate_bandwidth( + struct dc *dc, +- struct validate_context *context) ++ struct dc_state *context) + { + bool result = false; + +@@ -768,7 +768,7 @@ bool dce112_validate_bandwidth( + "%s: Bandwidth validation failed!", + __func__); + +- if (memcmp(&dc->current_context->bw.dce, ++ if (memcmp(&dc->current_state->bw.dce, + &context->bw.dce, sizeof(context->bw.dce))) { + struct log_entry log_entry; + dm_logger_open( +@@ -823,7 +823,7 @@ bool dce112_validate_bandwidth( + + enum dc_status resource_map_phy_clock_resources( + const struct dc *dc, +- struct validate_context *context, ++ struct dc_state *context, + struct dc_stream_state *stream) + { + +@@ -855,7 +855,7 @@ enum dc_status resource_map_phy_clock_resources( + } + + static bool dce112_validate_surface_sets( +- struct validate_context *context) ++ struct dc_state *context) + { + int i; + +@@ -876,7 +876,7 @@ static bool dce112_validate_surface_sets( + + enum dc_status dce112_add_stream_to_ctx( + struct dc *dc, +- struct validate_context *new_ctx, ++ struct dc_state *new_ctx, + struct dc_stream_state *dc_stream) + { + enum dc_status result = DC_ERROR_UNEXPECTED; +@@ -896,7 +896,7 @@ enum dc_status dce112_add_stream_to_ctx( + enum dc_status dce112_validate_guaranteed( + struct dc *dc, + struct dc_stream_state *stream, +- struct validate_context *context) ++ struct dc_state *context) + { + enum dc_status result = DC_ERROR_UNEXPECTED; + +@@ -927,7 +927,7 @@ enum dc_status dce112_validate_guaranteed( + + enum dc_status dce112_validate_global( + struct dc *dc, +- struct validate_context *context) ++ struct dc_state *context) + { + if (!dce112_validate_surface_sets(context)) + return DC_FAIL_SURFACE_VALIDATE; +diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h +index f1834bf..d5c19d3 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h ++++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h +@@ -39,21 +39,21 @@ enum dc_status dce112_validate_with_context( + struct dc *dc, + const struct dc_validation_set set[], + int set_count, +- struct validate_context *context, +- struct validate_context *old_context); ++ struct dc_state *context, ++ struct dc_state *old_context); + + enum dc_status dce112_validate_guaranteed( + struct dc *dc, + struct dc_stream_state *dc_stream, +- struct validate_context *context); ++ struct dc_state *context); + + bool dce112_validate_bandwidth( + struct dc *dc, +- struct validate_context *context); ++ struct dc_state *context); + + enum dc_status dce112_add_stream_to_ctx( + struct dc *dc, +- struct validate_context *new_ctx, ++ struct dc_state *new_ctx, + struct dc_stream_state *dc_stream); + + +diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +index 945ff7e..3160807 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +@@ -685,7 +685,7 @@ static void destruct(struct dce110_resource_pool *pool) + + static enum dc_status build_mapped_resource( + const struct dc *dc, +- struct validate_context *context, ++ struct dc_state *context, + struct dc_stream_state *stream) + { + enum dc_status status = DC_OK; +@@ -706,7 +706,7 @@ static enum dc_status build_mapped_resource( + + bool dce80_validate_bandwidth( + struct dc *dc, +- struct validate_context *context) ++ struct dc_state *context) + { + /* TODO implement when needed but for now hardcode max value*/ + context->bw.dce.dispclk_khz = 681000; +@@ -716,7 +716,7 @@ bool dce80_validate_bandwidth( + } + + static bool dce80_validate_surface_sets( +- struct validate_context *context) ++ struct dc_state *context) + { + int i; + +@@ -737,7 +737,7 @@ static bool dce80_validate_surface_sets( + + enum dc_status dce80_validate_global( + struct dc *dc, +- struct validate_context *context) ++ struct dc_state *context) + { + if (!dce80_validate_surface_sets(context)) + return DC_FAIL_SURFACE_VALIDATE; +@@ -748,7 +748,7 @@ enum dc_status dce80_validate_global( + enum dc_status dce80_validate_guaranteed( + struct dc *dc, + struct dc_stream_state *dc_stream, +- struct validate_context *context) ++ struct dc_state *context) + { + enum dc_status result = DC_ERROR_UNEXPECTED; + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +index 9c54cae..71ff1ce 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +@@ -793,7 +793,7 @@ static void undo_DEGVIDCN10_253_wa(struct dc *dc) + + static void ready_shared_resources(struct dc *dc) + { +- if (dc->current_context->stream_count == 0 && ++ if (dc->current_state->stream_count == 0 && + !dc->debug.disable_stutter) + undo_DEGVIDCN10_253_wa(dc); + } +@@ -815,7 +815,7 @@ static void apply_DEGVIDCN10_253_wa(struct dc *dc) + + static void optimize_shared_resources(struct dc *dc) + { +- if (dc->current_context->stream_count == 0 && ++ if (dc->current_state->stream_count == 0 && + !dc->debug.disable_stutter) + apply_DEGVIDCN10_253_wa(dc); + } +@@ -918,7 +918,7 @@ static void dcn10_init_hw(struct dc *dc) + + static enum dc_status dcn10_prog_pixclk_crtc_otg( + struct pipe_ctx *pipe_ctx, +- struct validate_context *context, ++ struct dc_state *context, + struct dc *dc) + { + struct dc_stream_state *stream = pipe_ctx->stream; +@@ -1008,7 +1008,7 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg( + static void reset_back_end_for_pipe( + struct dc *dc, + struct pipe_ctx *pipe_ctx, +- struct validate_context *context) ++ struct dc_state *context) + { + int i; + +@@ -1040,7 +1040,7 @@ static void reset_back_end_for_pipe( + &pipe_ctx->clock_source); + + for (i = 0; i < dc->res_pool->pipe_count; i++) +- if (&dc->current_context->res_ctx.pipe_ctx[i] == pipe_ctx) ++ if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx) + break; + + if (i == dc->res_pool->pipe_count) +@@ -1206,14 +1206,14 @@ static void dcn10_power_down_fe(struct dc *dc, int fe_idx) + + static void reset_hw_ctx_wrap( + struct dc *dc, +- struct validate_context *context) ++ struct dc_state *context) + { + int i; + + /* Reset Front End*/ + /* Lock*/ + for (i = 0; i < dc->res_pool->pipe_count; i++) { +- struct pipe_ctx *cur_pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[i]; ++ struct pipe_ctx *cur_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; + struct timing_generator *tg = cur_pipe_ctx->stream_res.tg; + + if (cur_pipe_ctx->stream) +@@ -1222,7 +1222,7 @@ static void reset_hw_ctx_wrap( + /* Disconnect*/ + for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { + struct pipe_ctx *pipe_ctx_old = +- &dc->current_context->res_ctx.pipe_ctx[i]; ++ &dc->current_state->res_ctx.pipe_ctx[i]; + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + + if (!pipe_ctx->stream || +@@ -1234,7 +1234,7 @@ static void reset_hw_ctx_wrap( + } + /* Unlock*/ + for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { +- struct pipe_ctx *cur_pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[i]; ++ struct pipe_ctx *cur_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; + struct timing_generator *tg = cur_pipe_ctx->stream_res.tg; + + if (cur_pipe_ctx->stream) +@@ -1244,7 +1244,7 @@ static void reset_hw_ctx_wrap( + /* Disable and Powerdown*/ + for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { + struct pipe_ctx *pipe_ctx_old = +- &dc->current_context->res_ctx.pipe_ctx[i]; ++ &dc->current_state->res_ctx.pipe_ctx[i]; + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + + /*if (!pipe_ctx_old->stream) +@@ -1263,7 +1263,7 @@ static void reset_hw_ctx_wrap( + /* Reset Back End*/ + for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { + struct pipe_ctx *pipe_ctx_old = +- &dc->current_context->res_ctx.pipe_ctx[i]; ++ &dc->current_state->res_ctx.pipe_ctx[i]; + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + + if (!pipe_ctx_old->stream) +@@ -1271,7 +1271,7 @@ static void reset_hw_ctx_wrap( + + if (!pipe_ctx->stream || + pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) +- reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_context); ++ reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); + } + } + +@@ -1943,7 +1943,7 @@ static void print_rq_dlg_ttu( + static void dcn10_power_on_fe( + struct dc *dc, + struct pipe_ctx *pipe_ctx, +- struct validate_context *context) ++ struct dc_state *context) + { + struct dc_plane_state *plane_state = pipe_ctx->plane_state; + struct dce_hwseq *hws = dc->hwseq; +@@ -2244,7 +2244,7 @@ static void dcn10_program_pte_vm(struct mem_input *mem_input, + static void update_dchubp_dpp( + struct dc *dc, + struct pipe_ctx *pipe_ctx, +- struct validate_context *context) ++ struct dc_state *context) + { + struct dce_hwseq *hws = dc->hwseq; + struct mem_input *mi = pipe_ctx->plane_res.mi; +@@ -2263,7 +2263,7 @@ static void update_dchubp_dpp( + pipe_ctx->pipe_idx, + pipe_ctx->stream_res.pix_clk_params.requested_pix_clk, + context->bw.dcn.calc_clk.dppclk_div); +- dc->current_context->bw.dcn.cur_clk.dppclk_div = ++ dc->current_state->bw.dcn.cur_clk.dppclk_div = + context->bw.dcn.calc_clk.dppclk_div; + context->bw.dcn.cur_clk.dppclk_div = context->bw.dcn.calc_clk.dppclk_div; + +@@ -2350,7 +2350,7 @@ static void update_dchubp_dpp( + static void program_all_pipe_in_tree( + struct dc *dc, + struct pipe_ctx *pipe_ctx, +- struct validate_context *context) ++ struct dc_state *context) + { + unsigned int ref_clk_mhz = dc->res_pool->ref_clock_inKhz/1000; + +@@ -2408,7 +2408,7 @@ static void program_all_pipe_in_tree( + + static void dcn10_pplib_apply_display_requirements( + struct dc *dc, +- struct validate_context *context) ++ struct dc_state *context) + { + struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; + +@@ -2437,7 +2437,7 @@ static void dcn10_apply_ctx_for_surface( + struct dc *dc, + const struct dc_stream_state *stream, + int num_planes, +- struct validate_context *context) ++ struct dc_state *context) + { + int i, be_idx; + +@@ -2457,7 +2457,7 @@ static void dcn10_apply_ctx_for_surface( + if (num_planes == 0) { + for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { + struct pipe_ctx *old_pipe_ctx = +- &dc->current_context->res_ctx.pipe_ctx[i]; ++ &dc->current_state->res_ctx.pipe_ctx[i]; + + if (old_pipe_ctx->stream_res.tg && old_pipe_ctx->stream_res.tg->inst == be_idx) { + old_pipe_ctx->stream_res.tg->funcs->set_blank(old_pipe_ctx->stream_res.tg, true); +@@ -2471,7 +2471,7 @@ static void dcn10_apply_ctx_for_surface( + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *old_pipe_ctx = +- &dc->current_context->res_ctx.pipe_ctx[i]; ++ &dc->current_state->res_ctx.pipe_ctx[i]; + + if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state) + continue; +@@ -2591,7 +2591,7 @@ static void dcn10_apply_ctx_for_surface( + + static void dcn10_set_bandwidth( + struct dc *dc, +- struct validate_context *context, ++ struct dc_state *context, + bool decrease_allowed) + { + struct pp_smu_display_requirement_rv *smu_req_cur = +@@ -2607,25 +2607,25 @@ static void dcn10_set_bandwidth( + return; + + if (decrease_allowed || context->bw.dcn.calc_clk.dispclk_khz +- > dc->current_context->bw.dcn.cur_clk.dispclk_khz) { ++ > dc->current_state->bw.dcn.cur_clk.dispclk_khz) { + dc->res_pool->display_clock->funcs->set_clock( + dc->res_pool->display_clock, + context->bw.dcn.calc_clk.dispclk_khz); +- dc->current_context->bw.dcn.cur_clk.dispclk_khz = ++ dc->current_state->bw.dcn.cur_clk.dispclk_khz = + context->bw.dcn.calc_clk.dispclk_khz; + } + if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_khz +- > dc->current_context->bw.dcn.cur_clk.dcfclk_khz) { ++ > dc->current_state->bw.dcn.cur_clk.dcfclk_khz) { + smu_req.hard_min_dcefclk_khz = + context->bw.dcn.calc_clk.dcfclk_khz; + } + if (decrease_allowed || context->bw.dcn.calc_clk.fclk_khz +- > dc->current_context->bw.dcn.cur_clk.fclk_khz) { ++ > dc->current_state->bw.dcn.cur_clk.fclk_khz) { + smu_req.hard_min_fclk_khz = context->bw.dcn.calc_clk.fclk_khz; + } + if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz +- > dc->current_context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz) { +- dc->current_context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz = ++ > dc->current_state->bw.dcn.cur_clk.dcfclk_deep_sleep_khz) { ++ dc->current_state->bw.dcn.calc_clk.dcfclk_deep_sleep_khz = + context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz; + context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz = + context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz; +@@ -2640,15 +2640,15 @@ static void dcn10_set_bandwidth( + + /* Decrease in freq is increase in period so opposite comparison for dram_ccm */ + if (decrease_allowed || context->bw.dcn.calc_clk.dram_ccm_us +- < dc->current_context->bw.dcn.cur_clk.dram_ccm_us) { +- dc->current_context->bw.dcn.calc_clk.dram_ccm_us = ++ < dc->current_state->bw.dcn.cur_clk.dram_ccm_us) { ++ dc->current_state->bw.dcn.calc_clk.dram_ccm_us = + context->bw.dcn.calc_clk.dram_ccm_us; + context->bw.dcn.cur_clk.dram_ccm_us = + context->bw.dcn.calc_clk.dram_ccm_us; + } + if (decrease_allowed || context->bw.dcn.calc_clk.min_active_dram_ccm_us +- < dc->current_context->bw.dcn.cur_clk.min_active_dram_ccm_us) { +- dc->current_context->bw.dcn.calc_clk.min_active_dram_ccm_us = ++ < dc->current_state->bw.dcn.cur_clk.min_active_dram_ccm_us) { ++ dc->current_state->bw.dcn.calc_clk.min_active_dram_ccm_us = + context->bw.dcn.calc_clk.min_active_dram_ccm_us; + context->bw.dcn.cur_clk.min_active_dram_ccm_us = + context->bw.dcn.calc_clk.min_active_dram_ccm_us; +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h +index 8bb09de..ca53dc1 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h +@@ -32,7 +32,7 @@ struct dc; + + void dcn10_hw_sequencer_construct(struct dc *dc); + extern void fill_display_configs( +- const struct validate_context *context, ++ const struct dc_state *context, + struct dm_pp_display_configuration *pp_display_cfg); + + #endif /* __DC_HWSS_DCN10_H__ */ +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +index d09ed13..fff86ad 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +@@ -850,7 +850,7 @@ static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx) + + static enum dc_status build_mapped_resource( + const struct dc *dc, +- struct validate_context *context, ++ struct dc_state *context, + struct dc_stream_state *stream) + { + enum dc_status status = DC_OK; +@@ -887,7 +887,7 @@ static enum dc_status build_mapped_resource( + + enum dc_status dcn10_add_stream_to_ctx( + struct dc *dc, +- struct validate_context *new_ctx, ++ struct dc_state *new_ctx, + struct dc_stream_state *dc_stream) + { + enum dc_status result = DC_ERROR_UNEXPECTED; +@@ -907,7 +907,7 @@ enum dc_status dcn10_add_stream_to_ctx( + enum dc_status dcn10_validate_guaranteed( + struct dc *dc, + struct dc_stream_state *dc_stream, +- struct validate_context *context) ++ struct dc_state *context) + { + enum dc_status result = DC_ERROR_UNEXPECTED; + +@@ -935,7 +935,7 @@ enum dc_status dcn10_validate_guaranteed( + } + + static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer( +- struct validate_context *context, ++ struct dc_state *context, + const struct resource_pool *pool, + struct dc_stream_state *stream) + { +diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h +index bd1a636..71eb985 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h +@@ -80,7 +80,7 @@ void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable); + #include "transform.h" + + struct resource_pool; +-struct validate_context; ++struct dc_state; + struct resource_context; + + struct resource_funcs { +@@ -91,18 +91,18 @@ struct resource_funcs { + enum dc_status (*validate_guaranteed)( + struct dc *dc, + struct dc_stream_state *stream, +- struct validate_context *context); ++ struct dc_state *context); + + bool (*validate_bandwidth)( + struct dc *dc, +- struct validate_context *context); ++ struct dc_state *context); + + enum dc_status (*validate_global)( + struct dc *dc, +- struct validate_context *context); ++ struct dc_state *context); + + struct pipe_ctx *(*acquire_idle_pipe_for_layer)( +- struct validate_context *context, ++ struct dc_state *context, + const struct resource_pool *pool, + struct dc_stream_state *stream); + +@@ -110,7 +110,7 @@ struct resource_funcs { + + enum dc_status (*add_stream_to_ctx)( + struct dc *dc, +- struct validate_context *new_ctx, ++ struct dc_state *new_ctx, + struct dc_stream_state *dc_stream); + }; + +@@ -252,7 +252,7 @@ union bw_context { + struct dce_bw_output dce; + }; + +-struct validate_context { ++struct dc_state { + struct dc_stream_state *streams[MAX_PIPES]; + struct dc_stream_status stream_status[MAX_PIPES]; + uint8_t stream_count; +diff --git a/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h +index 6a205b0..ae2399f 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h +@@ -34,7 +34,7 @@ + + struct pipe_ctx; + struct dc; +-struct validate_context; ++struct dc_state; + struct dce_bw_output; + + enum bw_calcs_version { +diff --git a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h +index 58744fe8..1e231f6 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h +@@ -35,7 +35,7 @@ + #include "../dml/display_mode_lib.h" + + struct dc; +-struct validate_context; ++struct dc_state; + + /******************************************************************************* + * DCN data structures. +@@ -621,7 +621,7 @@ extern const struct dcn_ip_params dcn10_ip_defaults; + + bool dcn_validate_bandwidth( + struct dc *dc, +- struct validate_context *context); ++ struct dc_state *context); + + unsigned int dcn_find_dcfclk_suits_all( + const struct dc *dc, +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +index 01e4261..aae7629 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +@@ -49,7 +49,7 @@ struct dce_hwseq { + }; + + struct pipe_ctx; +-struct validate_context; ++struct dc_state; + struct dchub_init_data; + struct dc_static_screen_events; + struct resource_pool; +@@ -60,16 +60,16 @@ struct hw_sequencer_funcs { + void (*init_hw)(struct dc *dc); + + enum dc_status (*apply_ctx_to_hw)( +- struct dc *dc, struct validate_context *context); ++ struct dc *dc, struct dc_state *context); + + void (*reset_hw_ctx_wrap)( +- struct dc *dc, struct validate_context *context); ++ struct dc *dc, struct dc_state *context); + + void (*apply_ctx_for_surface)( + struct dc *dc, + const struct dc_stream_state *stream, + int num_planes, +- struct validate_context *context); ++ struct dc_state *context); + + void (*set_plane_config)( + const struct dc *dc, +@@ -127,7 +127,7 @@ struct hw_sequencer_funcs { + + void (*power_on_front_end)(struct dc *dc, + struct pipe_ctx *pipe, +- struct validate_context *context); ++ struct dc_state *context); + + void (*update_info_frame)(struct pipe_ctx *pipe_ctx); + +@@ -145,7 +145,7 @@ struct hw_sequencer_funcs { + + void (*set_bandwidth)( + struct dc *dc, +- struct validate_context *context, ++ struct dc_state *context, + bool decrease_allowed); + + void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes, +@@ -159,7 +159,7 @@ struct hw_sequencer_funcs { + + enum dc_status (*prog_pixclk_crtc_otg)( + struct pipe_ctx *pipe_ctx, +- struct validate_context *context, ++ struct dc_state *context, + struct dc *dc); + + void (*setup_stereo)( +diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h +index ebc0f5b..41437da 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/resource.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h +@@ -81,14 +81,14 @@ void dc_destroy_resource_pool(struct dc *dc); + + enum dc_status resource_map_pool_resources( + const struct dc *dc, +- struct validate_context *context, ++ struct dc_state *context, + struct dc_stream_state *stream); + + bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx); + + enum dc_status resource_build_scaling_params_for_context( + const struct dc *dc, +- struct validate_context *context); ++ struct dc_state *context); + + void resource_build_info_frame(struct pipe_ctx *pipe_ctx); + +@@ -122,7 +122,7 @@ bool resource_attach_surfaces_to_context( + struct dc_plane_state *const *plane_state, + int surface_count, + struct dc_stream_state *dc_stream, +- struct validate_context *context, ++ struct dc_state *context, + const struct resource_pool *pool); + + struct pipe_ctx *find_idle_secondary_pipe( +@@ -130,31 +130,31 @@ struct pipe_ctx *find_idle_secondary_pipe( + const struct resource_pool *pool); + + bool resource_is_stream_unchanged( +- struct validate_context *old_context, struct dc_stream_state *stream); ++ struct dc_state *old_context, struct dc_stream_state *stream); + + bool resource_validate_attach_surfaces( + const struct dc_validation_set set[], + int set_count, +- const struct validate_context *old_context, +- struct validate_context *context, ++ const struct dc_state *old_context, ++ struct dc_state *context, + const struct resource_pool *pool); + + void validate_guaranteed_copy_streams( +- struct validate_context *context, ++ struct dc_state *context, + int max_streams); + + void resource_validate_ctx_update_pointer_after_copy( +- const struct validate_context *src_ctx, +- struct validate_context *dst_ctx); ++ const struct dc_state *src_ctx, ++ struct dc_state *dst_ctx); + + enum dc_status resource_map_clock_resources( + const struct dc *dc, +- struct validate_context *context, ++ struct dc_state *context, + struct dc_stream_state *stream); + + enum dc_status resource_map_phy_clock_resources( + const struct dc *dc, +- struct validate_context *context, ++ struct dc_state *context, + struct dc_stream_state *stream); + + bool pipe_need_reprogram( +diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c +index e3a12f3..7cce284 100644 +--- a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c ++++ b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c +@@ -214,7 +214,7 @@ bool dce110_vblank_set( + uint8_t pipe_offset = dal_irq_src - IRQ_TYPE_VBLANK; + + struct timing_generator *tg = +- core_dc->current_context->res_ctx.pipe_ctx[pipe_offset].stream_res.tg; ++ core_dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg; + + if (enable) { + if (!tg->funcs->arm_vert_intr(tg, 2)) { +diff --git a/drivers/gpu/drm/amd/display/include/logger_interface.h b/drivers/gpu/drm/amd/display/include/logger_interface.h +index 93c8556..6641e80 100644 +--- a/drivers/gpu/drm/amd/display/include/logger_interface.h ++++ b/drivers/gpu/drm/amd/display/include/logger_interface.h +@@ -32,7 +32,7 @@ struct dc_context; + struct dc_link; + struct dc_surface_update; + struct resource_context; +-struct validate_context; ++struct dc_state; + + /* + * +@@ -93,7 +93,7 @@ void context_timing_trace( + + void context_clock_trace( + struct dc *dc, +- struct validate_context *context); ++ struct dc_state *context); + + /* Any function which is empty or have incomplete implementation should be + * marked by this macro. +-- +2.7.4 + |