diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0981-drm-amd-display-Log-OTG-registers-with-dcn10-hw-stat.patch')
-rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0981-drm-amd-display-Log-OTG-registers-with-dcn10-hw-stat.patch | 184 |
1 files changed, 184 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0981-drm-amd-display-Log-OTG-registers-with-dcn10-hw-stat.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0981-drm-amd-display-Log-OTG-registers-with-dcn10-hw-stat.patch new file mode 100644 index 00000000..3384ee5e --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0981-drm-amd-display-Log-OTG-registers-with-dcn10-hw-stat.patch @@ -0,0 +1,184 @@ +From d8ff5cb7e51fc203f08ddf11a544f07f92b09b29 Mon Sep 17 00:00:00 2001 +From: Corbin McElhanney <corbin.mcelhanney@amd.com> +Date: Wed, 16 Aug 2017 11:49:07 -0400 +Subject: [PATCH 0981/4131] drm/amd/display: Log OTG registers with dcn10 hw + state + +Signed-off-by: Corbin McElhanney <corbin.mcelhanney@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Harry Wentland <Harry.Wentland@amd.com> +--- + .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 33 +++++++++++++++++ + .../amd/display/dc/dcn10/dcn10_timing_generator.c | 42 ++++++++++++++++++++++ + .../amd/display/dc/dcn10/dcn10_timing_generator.h | 25 +++++++++++++ + 3 files changed, 100 insertions(+) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +index f0e49d1..ddfa6a8 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +@@ -32,6 +32,7 @@ + #include "dce/dce_hwseq.h" + #include "abm.h" + #include "dcn10/dcn10_mem_input.h" ++#include "dcn10/dcn10_timing_generator.h" + #include "dcn10/dcn10_dpp.h" + #include "dcn10/dcn10_mpc.h" + #include "timing_generator.h" +@@ -200,6 +201,38 @@ static void dcn10_log_hw_state(struct dc *dc) + } + DTN_INFO("\n"); + ++ DTN_INFO("OTG:\t v_bs \t v_be \t v_ss \t v_se \t vpol \t vmax \t vmin \t " ++ "h_bs \t h_be \t h_ss \t h_se \t hpol \t htot \t vtot \t underflow\n"); ++ ++ for (i = 0; i < pool->pipe_count; i++) { ++ struct timing_generator *tg = pool->timing_generators[i]; ++ struct dcn_otg_state s; ++ ++ tgn10_read_otg_state(DCN10TG_FROM_TG(tg), &s); ++ ++ DTN_INFO("[%d]:\t %d \t %d \t %d \t %d \t " ++ "%d \t %d \t %d \t %d \t %d \t %d \t " ++ "%d \t %d \t %d \t %d \t %d \t ", ++ i, ++ s.v_blank_start, ++ s.v_blank_end, ++ s.v_sync_a_start, ++ s.v_sync_a_end, ++ s.v_sync_a_pol, ++ s.v_total_max, ++ s.v_total_min, ++ s.h_blank_start, ++ s.h_blank_end, ++ s.h_sync_a_start, ++ s.h_sync_a_end, ++ s.h_sync_a_pol, ++ s.h_total, ++ s.v_total, ++ s.underflow_occurred_status); ++ DTN_INFO("\n"); ++ } ++ DTN_INFO("\n"); ++ + log_mpc_crc(dc); + + DTN_INFO_END(); +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c +index 941e012..6a5f268 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c +@@ -1090,6 +1090,48 @@ static bool tgn10_is_stereo_left_eye(struct timing_generator *tg) + return ret; + } + ++void tgn10_read_otg_state(struct dcn10_timing_generator *tgn10, ++ struct dcn_otg_state *s) ++{ ++ REG_GET_2(OTG_V_BLANK_START_END, ++ OTG_V_BLANK_START, &s->v_blank_start, ++ OTG_V_BLANK_END, &s->v_blank_end); ++ ++ REG_GET(OTG_V_SYNC_A_CNTL, ++ OTG_V_SYNC_A_POL, &s->v_sync_a_pol); ++ ++ REG_GET(OTG_V_TOTAL, ++ OTG_V_TOTAL, &s->v_total); ++ ++ REG_GET(OTG_V_TOTAL_MAX, ++ OTG_V_TOTAL_MAX, &s->v_total_max); ++ ++ REG_GET(OTG_V_TOTAL_MIN, ++ OTG_V_TOTAL_MIN, &s->v_total_min); ++ ++ REG_GET_2(OTG_V_SYNC_A, ++ OTG_V_SYNC_A_START, &s->v_sync_a_start, ++ OTG_V_SYNC_A_END, &s->v_sync_a_end); ++ ++ REG_GET_2(OTG_H_BLANK_START_END, ++ OTG_H_BLANK_START, &s->h_blank_start, ++ OTG_H_BLANK_END, &s->h_blank_end); ++ ++ REG_GET_2(OTG_H_SYNC_A, ++ OTG_H_SYNC_A_START, &s->h_sync_a_start, ++ OTG_H_SYNC_A_END, &s->h_sync_a_end); ++ ++ REG_GET(OTG_H_SYNC_A_CNTL, ++ OTG_H_SYNC_A_POL, &s->h_sync_a_pol); ++ ++ REG_GET(OTG_H_TOTAL, ++ OTG_H_TOTAL, &s->h_total); ++ ++ REG_GET(OPTC_INPUT_GLOBAL_CONTROL, ++ OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status); ++} ++ ++ + static struct timing_generator_funcs dcn10_tg_funcs = { + .validate_timing = tgn10_validate_timing, + .program_timing = tgn10_program_timing, +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h +index 747e821..6548893 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h +@@ -67,6 +67,7 @@ + SRI(OTG_CLOCK_CONTROL, OTG, inst),\ + SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\ + SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\ ++ SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\ + SRI(OPPBUF_CONTROL, OPPBUF, inst),\ + SRI(OPPBUF_3D_PARAMETERS_0, OPPBUF, inst),\ + SRI(CONTROL, VTG, inst),\ +@@ -121,6 +122,7 @@ struct dcn_tg_registers { + uint32_t OTG_CLOCK_CONTROL; + uint32_t OPTC_INPUT_CLOCK_CONTROL; + uint32_t OPTC_DATA_SOURCE_SELECT; ++ uint32_t OPTC_INPUT_GLOBAL_CONTROL; + uint32_t OPPBUF_CONTROL; + uint32_t OPPBUF_3D_PARAMETERS_0; + uint32_t CONTROL; +@@ -204,6 +206,7 @@ struct dcn_tg_registers { + SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\ + SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\ + SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\ ++ SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\ + SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, mask_sh),\ + SF(OPPBUF0_OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE1_SIZE, mask_sh),\ + SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\ +@@ -310,6 +313,7 @@ struct dcn_tg_registers { + type OPTC_INPUT_CLK_GATE_DIS;\ + type OPTC_SRC_SEL;\ + type OPTC_SEG0_SRC_SEL;\ ++ type OPTC_UNDERFLOW_OCCURRED_STATUS;\ + type OPPBUF_ACTIVE_WIDTH;\ + type OPPBUF_3D_VACT_SPACE1_SIZE;\ + type VTG0_ENABLE;\ +@@ -346,4 +350,25 @@ struct dcn10_timing_generator { + + void dcn10_timing_generator_init(struct dcn10_timing_generator *tg); + ++struct dcn_otg_state { ++ uint32_t v_blank_start; ++ uint32_t v_blank_end; ++ uint32_t v_sync_a_pol; ++ uint32_t v_total; ++ uint32_t v_total_max; ++ uint32_t v_total_min; ++ uint32_t v_sync_a_start; ++ uint32_t v_sync_a_end; ++ uint32_t h_blank_start; ++ uint32_t h_blank_end; ++ uint32_t h_sync_a_start; ++ uint32_t h_sync_a_end; ++ uint32_t h_sync_a_pol; ++ uint32_t h_total; ++ uint32_t underflow_occurred_status; ++}; ++ ++void tgn10_read_otg_state(struct dcn10_timing_generator *tgn10, ++ struct dcn_otg_state *s); ++ + #endif /* __DC_TIMING_GENERATOR_DCN10_H__ */ +-- +2.7.4 + |