diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0929-drm-amd-powerplay-Port-vega10_hwmgr.c-over-to-PP_CAP.patch')
-rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0929-drm-amd-powerplay-Port-vega10_hwmgr.c-over-to-PP_CAP.patch | 263 |
1 files changed, 263 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0929-drm-amd-powerplay-Port-vega10_hwmgr.c-over-to-PP_CAP.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0929-drm-amd-powerplay-Port-vega10_hwmgr.c-over-to-PP_CAP.patch new file mode 100644 index 00000000..5896c39b --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0929-drm-amd-powerplay-Port-vega10_hwmgr.c-over-to-PP_CAP.patch @@ -0,0 +1,263 @@ +From 1b7d69e99c7f35e177415c9e243ef6c3b7aaaa86 Mon Sep 17 00:00:00 2001 +From: Chaudhary Amit Kumar <chaudharyamit.kumar@amd.com> +Date: Wed, 17 Oct 2018 17:05:48 +0530 +Subject: [PATCH 0929/4131] drm/amd/powerplay: Port vega10_hwmgr.c over to + PP_CAP + +Replace and cleanup lengthy phm_cap_enabled() sequences +with PP_CAP. + +Signed-off-by: Tom St Denis <tom.stdenis@amd.com> +Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> +Signed-off-by: Chaudhary Amit Kumar <chaudharyamit.kumar@amd.com> +--- + drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 91 ++++++++-------------- + 1 file changed, 32 insertions(+), 59 deletions(-) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +index 5762d6d..62ba170 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +@@ -381,12 +381,10 @@ static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr) + if (!data->registry_data.socclk_dpm_key_disabled) + data->smu_features[GNLD_DPM_SOCCLK].supported = true; + +- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_UVDDPM)) ++ if (PP_CAP(PHM_PlatformCaps_UVDDPM)) + data->smu_features[GNLD_DPM_UVD].supported = true; + +- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_VCEDPM)) ++ if (PP_CAP(PHM_PlatformCaps_VCEDPM)) + data->smu_features[GNLD_DPM_VCE].supported = true; + + if (!data->registry_data.pcie_dpm_key_disabled) +@@ -395,9 +393,8 @@ static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr) + if (!data->registry_data.dcefclk_dpm_key_disabled) + data->smu_features[GNLD_DPM_DCEFCLK].supported = true; + +- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_SclkDeepSleep) && +- data->registry_data.sclk_deep_sleep_support) { ++ if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep) && ++ data->registry_data.sclk_deep_sleep_support) { + data->smu_features[GNLD_DS_GFXCLK].supported = true; + data->smu_features[GNLD_DS_SOCCLK].supported = true; + data->smu_features[GNLD_DS_LCLK].supported = true; +@@ -497,8 +494,7 @@ static int vega10_get_evv_voltages(struct pp_hwmgr *hwmgr) + + if (!vega10_get_socclk_for_voltage_evv(hwmgr, + table_info->vddc_lookup_table, vv_id, &sclk)) { +- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_ClockStretcher)) { ++ if (PP_CAP(PHM_PlatformCaps_ClockStretcher)) { + for (j = 1; j < socclk_table->count; j++) { + if (socclk_table->entries[j].clk == sclk && + socclk_table->entries[j].cks_enable == 0) { +@@ -809,8 +805,7 @@ static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr) + } + + /* VDDCI_MEM */ +- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_ControlVDDCI)) { ++ if (PP_CAP(PHM_PlatformCaps_ControlVDDCI)) { + if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr, + VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT)) + data->vddci_control = VEGA10_VOLTAGE_CONTROL_BY_GPIO; +@@ -1382,10 +1377,8 @@ static int vega10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) + memcpy(&(data->golden_dpm_table), &(data->dpm_table), + sizeof(struct vega10_dpm_table)); + +- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_ODNinACSupport) || +- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_ODNinDCSupport)) { ++ if (PP_CAP(PHM_PlatformCaps_ODNinACSupport) || ++ PP_CAP(PHM_PlatformCaps_ODNinDCSupport)) { + data->odn_dpm_table.odn_core_clock_dpm_levels. + number_of_performance_levels = data->dpm_table.gfx_table.count; + for (i = 0; i < data->dpm_table.gfx_table.count; i++) { +@@ -2332,9 +2325,8 @@ static int vega10_populate_gpio_parameters(struct pp_hwmgr *hwmgr) + + result = pp_atomfwctrl_get_gpio_information(hwmgr, &gpio_params); + if (!result) { +- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_RegulatorHot) && +- (data->registry_data.regulator_hot_gpio_support)) { ++ if (PP_CAP(PHM_PlatformCaps_RegulatorHot) && ++ data->registry_data.regulator_hot_gpio_support) { + pp_table->VR0HotGpio = gpio_params.ucVR0HotGpio; + pp_table->VR0HotPolarity = gpio_params.ucVR0HotPolarity; + pp_table->VR1HotGpio = gpio_params.ucVR1HotGpio; +@@ -2346,9 +2338,8 @@ static int vega10_populate_gpio_parameters(struct pp_hwmgr *hwmgr) + pp_table->VR1HotPolarity = 0; + } + +- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_AutomaticDCTransition) && +- (data->registry_data.ac_dc_switch_gpio_support)) { ++ if (PP_CAP(PHM_PlatformCaps_AutomaticDCTransition) && ++ data->registry_data.ac_dc_switch_gpio_support) { + pp_table->AcDcGpio = gpio_params.ucAcDcGpio; + pp_table->AcDcPolarity = gpio_params.ucAcDcPolarity; + } else { +@@ -2646,8 +2637,7 @@ static int vega10_enable_vrhot_feature(struct pp_hwmgr *hwmgr) + struct vega10_hwmgr *data = + (struct vega10_hwmgr *)(hwmgr->backend); + +- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_RegulatorHot)) { ++ if (PP_CAP(PHM_PlatformCaps_RegulatorHot)) { + if (data->smu_features[GNLD_VR0HOT].supported) { + PP_ASSERT_WITH_CODE( + !vega10_enable_smc_features(hwmgr->smumgr, +@@ -2861,8 +2851,7 @@ static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap) + data->vbios_boot_state.bsoc_vddc_lock = false; + } + +- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_Falcon_QuickTransition)) { ++ if (PP_CAP(PHM_PlatformCaps_Falcon_QuickTransition)) { + if (data->smu_features[GNLD_ACDC].supported) { + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, + true, data->smu_features[GNLD_ACDC].smu_feature_bitmap), +@@ -2905,8 +2894,7 @@ static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr) + "Failed to initialize SMC table!", + result = tmp_result); + +- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_ThermalController)) { ++ if (PP_CAP(PHM_PlatformCaps_ThermalController)) { + tmp_result = vega10_enable_thermal_protection(hwmgr); + PP_ASSERT_WITH_CODE(!tmp_result, + "Failed to enable thermal protection!", +@@ -3141,8 +3129,7 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, + minimum_clocks.engineClock = hwmgr->display_config.min_core_set_clock; + minimum_clocks.memoryClock = hwmgr->display_config.min_mem_set_clock; + +- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_StablePState)) { ++ if (PP_CAP(PHM_PlatformCaps_StablePState)) { + PP_ASSERT_WITH_CODE( + data->registry_data.stable_pstate_sclk_dpm_percentage >= 1 && + data->registry_data.stable_pstate_sclk_dpm_percentage <= 100, +@@ -3207,10 +3194,8 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, + disable_mclk_switching_for_frame_lock = phm_cap_enabled( + hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_DisableMclkSwitchingForFrameLock); +- disable_mclk_switching_for_vr = phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_DisableMclkSwitchForVR); +- force_mclk_high = phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_ForceMclkHigh); ++ disable_mclk_switching_for_vr = PP_CAP(PHM_PlatformCaps_DisableMclkSwitchForVR); ++ force_mclk_high = PP_CAP(PHM_PlatformCaps_ForceMclkHigh); + + if (info.display_count == 0) + disable_mclk_switching = false; +@@ -3264,8 +3249,7 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, + vega10_ps->performance_levels[1].mem_clock; + } + +- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_StablePState)) { ++ if (PP_CAP(PHM_PlatformCaps_StablePState)) { + for (i = 0; i < vega10_ps->performance_level_count; i++) { + vega10_ps->performance_levels[i].gfx_clock = stable_pstate_sclk; + vega10_ps->performance_levels[i].mem_clock = stable_pstate_mclk; +@@ -3297,10 +3281,8 @@ static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, co + + data->need_update_dpm_table = 0; + +- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_ODNinACSupport) || +- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_ODNinDCSupport)) { ++ if (PP_CAP(PHM_PlatformCaps_ODNinACSupport) || ++ PP_CAP(PHM_PlatformCaps_ODNinDCSupport)) { + for (i = 0; i < sclk_table->count; i++) { + if (sclk == sclk_table->dpm_levels[i].value) + break; +@@ -3384,10 +3366,8 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels( + uint32_t dpm_count, clock_percent; + uint32_t i; + +- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_ODNinACSupport) || +- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_ODNinDCSupport)) { ++ if (PP_CAP(PHM_PlatformCaps_ODNinACSupport) || ++ PP_CAP(PHM_PlatformCaps_ODNinDCSupport)) { + + if (!data->need_update_dpm_table && + !data->apply_optimized_settings && +@@ -3452,10 +3432,8 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels( + dpm_table-> + gfx_table.dpm_levels[dpm_table->gfx_table.count - 1]. + value = sclk; +- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_OD6PlusinACSupport) || +- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_OD6PlusinDCSupport)) { ++ if (PP_CAP(PHM_PlatformCaps_OD6PlusinACSupport) || ++ PP_CAP(PHM_PlatformCaps_OD6PlusinDCSupport)) { + /* Need to do calculation based on the golden DPM table + * as the Heatmap GPU Clock axis is also based on + * the default values +@@ -3509,10 +3487,8 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels( + mem_table.dpm_levels[dpm_table->mem_table.count - 1]. + value = mclk; + +- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_OD6PlusinACSupport) || +- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_OD6PlusinDCSupport)) { ++ if (PP_CAP(PHM_PlatformCaps_OD6PlusinACSupport) || ++ PP_CAP(PHM_PlatformCaps_OD6PlusinDCSupport)) { + + PP_ASSERT_WITH_CODE( + golden_dpm_table->mem_table.dpm_levels +@@ -3843,9 +3819,8 @@ static int vega10_update_sclk_threshold(struct pp_hwmgr *hwmgr) + int result = 0; + uint32_t low_sclk_interrupt_threshold = 0; + +- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_SclkThrottleLowNotification) +- && (hwmgr->gfx_arbiter.sclk_threshold != ++ if (PP_CAP(PHM_PlatformCaps_SclkThrottleLowNotification) && ++ (hwmgr->gfx_arbiter.sclk_threshold != + data->low_sclk_interrupt_threshold)) { + data->low_sclk_interrupt_threshold = + hwmgr->gfx_arbiter.sclk_threshold; +@@ -4256,8 +4231,7 @@ static int vega10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode) + result = vega10_fan_ctrl_set_fan_speed_percent(hwmgr, 100); + break; + case AMD_FAN_CTRL_MANUAL: +- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_MicrocodeFanControl)) ++ if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) + result = vega10_fan_ctrl_stop_smc_fan_control(hwmgr); + break; + case AMD_FAN_CTRL_AUTO: +@@ -4801,7 +4775,7 @@ vega10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmg + if (data->display_timing.num_existing_displays != info.display_count) + is_update_required = true; + +- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) { ++ if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep)) { + if (data->display_timing.min_clock_in_sr != hwmgr->display_config.min_core_set_clock_in_sr) + is_update_required = true; + } +@@ -4818,8 +4792,7 @@ static int vega10_disable_dpm_tasks(struct pp_hwmgr *hwmgr) + "DPM is not running right now, no need to disable DPM!", + return 0); + +- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_ThermalController)) ++ if (PP_CAP(PHM_PlatformCaps_ThermalController)) + vega10_disable_thermal_protection(hwmgr); + + tmp_result = vega10_disable_power_containment(hwmgr); +-- +2.7.4 + |