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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0926-drm-amd-powerplay-Introduction-of-bitmask-macros-for.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0926-drm-amd-powerplay-Introduction-of-bitmask-macros-for.patch42
1 files changed, 42 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0926-drm-amd-powerplay-Introduction-of-bitmask-macros-for.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0926-drm-amd-powerplay-Introduction-of-bitmask-macros-for.patch
new file mode 100644
index 00000000..21b6526e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0926-drm-amd-powerplay-Introduction-of-bitmask-macros-for.patch
@@ -0,0 +1,42 @@
+From 41b781d7d22d615c83bd8d9c25afa4abee5b1b55 Mon Sep 17 00:00:00 2001
+From: Tom St Denis <tom.stdenis@amd.com>
+Date: Wed, 6 Sep 2017 08:04:10 -0400
+Subject: [PATCH 0926/4131] drm/amd/powerplay: Introduction of bitmask macros
+ for registers
+
+Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
+Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
+---
+ drivers/gpu/drm/amd/include/cgs_common.h | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/include/cgs_common.h b/drivers/gpu/drm/amd/include/cgs_common.h
+index 0214f63..92eaa81 100644
+--- a/drivers/gpu/drm/amd/include/cgs_common.h
++++ b/drivers/gpu/drm/amd/include/cgs_common.h
+@@ -310,6 +310,22 @@ typedef uint32_t (*cgs_read_ind_register_t)(struct cgs_device *cgs_device, enum
+ typedef void (*cgs_write_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space,
+ unsigned index, uint32_t value);
+
++#define CGS_REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
++#define CGS_REG_FIELD_MASK(reg, field) reg##__##field##_MASK
++
++#define CGS_REG_SET_FIELD(orig_val, reg, field, field_val) \
++ (((orig_val) & ~CGS_REG_FIELD_MASK(reg, field)) | \
++ (CGS_REG_FIELD_MASK(reg, field) & ((field_val) << CGS_REG_FIELD_SHIFT(reg, field))))
++
++#define CGS_REG_GET_FIELD(value, reg, field) \
++ (((value) & CGS_REG_FIELD_MASK(reg, field)) >> CGS_REG_FIELD_SHIFT(reg, field))
++
++#define CGS_WREG32_FIELD(device, reg, field, val) \
++ cgs_write_register(device, mm##reg, (cgs_read_register(device, mm##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field))
++
++#define CGS_WREG32_FIELD_IND(device, space, reg, field, val) \
++ cgs_write_ind_register(device, space, ix##reg, (cgs_read_ind_register(device, space, ix##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field))
++
+ /**
+ * cgs_get_pci_resource() - provide access to a device resource (PCI BAR)
+ * @cgs_device: opaque device handle
+--
+2.7.4
+