diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0901-drm-amd-amdgpu-Tidy-up-gmc_v9_0_hw_init.patch')
-rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0901-drm-amd-amdgpu-Tidy-up-gmc_v9_0_hw_init.patch | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0901-drm-amd-amdgpu-Tidy-up-gmc_v9_0_hw_init.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0901-drm-amd-amdgpu-Tidy-up-gmc_v9_0_hw_init.patch new file mode 100644 index 00000000..1066081f --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0901-drm-amd-amdgpu-Tidy-up-gmc_v9_0_hw_init.patch @@ -0,0 +1,42 @@ +From 423ca721841593109e0bc2100f0ebfaa65c2a2ec Mon Sep 17 00:00:00 2001 +From: Tom St Denis <tom.stdenis@amd.com> +Date: Fri, 1 Sep 2017 09:53:44 -0400 +Subject: [PATCH 0901/4131] drm/amd/amdgpu: Tidy up gmc_v9_0_hw_init() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Tom St Denis <tom.stdenis@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Reviewed-by: Christian König <christian.koenig@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 10 ++-------- + 1 file changed, 2 insertions(+), 8 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +index 2446b19..eafd0e7 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +@@ -761,17 +761,11 @@ static int gmc_v9_0_hw_init(void *handle) + gmc_v9_0_init_golden_registers(adev); + + if (adev->mode_info.num_crtc) { +- u32 tmp; +- + /* Lockout access through VGA aperture*/ +- tmp = RREG32_SOC15(DCE, 0, mmVGA_HDP_CONTROL); +- tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); +- WREG32_SOC15(DCE, 0, mmVGA_HDP_CONTROL, tmp); ++ WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); + + /* disable VGA render */ +- tmp = RREG32_SOC15(DCE, 0, mmVGA_RENDER_CONTROL); +- tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); +- WREG32_SOC15(DCE, 0, mmVGA_RENDER_CONTROL, tmp); ++ WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); + } + + r = gmc_v9_0_gart_enable(adev); +-- +2.7.4 + |