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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0899-drm-amd-amdgpu-Simplify-gmc_v9_0_vm_fault_interrupt_.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0899-drm-amd-amdgpu-Simplify-gmc_v9_0_vm_fault_interrupt_.patch92
1 files changed, 92 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0899-drm-amd-amdgpu-Simplify-gmc_v9_0_vm_fault_interrupt_.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0899-drm-amd-amdgpu-Simplify-gmc_v9_0_vm_fault_interrupt_.patch
new file mode 100644
index 00000000..65243766
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0899-drm-amd-amdgpu-Simplify-gmc_v9_0_vm_fault_interrupt_.patch
@@ -0,0 +1,92 @@
+From af9a15927e103793a6ff09c642599568ca47c9b0 Mon Sep 17 00:00:00 2001
+From: Tom St Denis <tom.stdenis@amd.com>
+Date: Fri, 1 Sep 2017 09:27:31 -0400
+Subject: [PATCH 0899/4131] drm/amd/amdgpu: Simplify
+ gmc_v9_0_vm_fault_interrupt_state()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Christian K├Ânig <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 51 ++++++++++++-----------------------
+ 1 file changed, 17 insertions(+), 34 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index a1d7142..92574ee 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -77,7 +77,7 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
+ enum amdgpu_interrupt_state state)
+ {
+ struct amdgpu_vmhub *hub;
+- u32 tmp, reg, bits, i;
++ u32 tmp, reg, bits, i, j;
+
+ bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+ VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+@@ -89,43 +89,26 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
+
+ switch (state) {
+ case AMDGPU_IRQ_STATE_DISABLE:
+- /* MM HUB */
+- hub = &adev->vmhub[AMDGPU_MMHUB];
+- for (i = 0; i< 16; i++) {
+- reg = hub->vm_context0_cntl + i;
+- tmp = RREG32(reg);
+- tmp &= ~bits;
+- WREG32(reg, tmp);
+- }
+-
+- /* GFX HUB */
+- hub = &adev->vmhub[AMDGPU_GFXHUB];
+- for (i = 0; i < 16; i++) {
+- reg = hub->vm_context0_cntl + i;
+- tmp = RREG32(reg);
+- tmp &= ~bits;
+- WREG32(reg, tmp);
++ for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
++ hub = &adev->vmhub[j];
++ for (i = 0; i < 16; i++) {
++ reg = hub->vm_context0_cntl + i;
++ tmp = RREG32(reg);
++ tmp &= ~bits;
++ WREG32(reg, tmp);
++ }
+ }
+ break;
+ case AMDGPU_IRQ_STATE_ENABLE:
+- /* MM HUB */
+- hub = &adev->vmhub[AMDGPU_MMHUB];
+- for (i = 0; i< 16; i++) {
+- reg = hub->vm_context0_cntl + i;
+- tmp = RREG32(reg);
+- tmp |= bits;
+- WREG32(reg, tmp);
++ for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
++ hub = &adev->vmhub[j];
++ for (i = 0; i < 16; i++) {
++ reg = hub->vm_context0_cntl + i;
++ tmp = RREG32(reg);
++ tmp |= bits;
++ WREG32(reg, tmp);
++ }
+ }
+-
+- /* GFX HUB */
+- hub = &adev->vmhub[AMDGPU_GFXHUB];
+- for (i = 0; i < 16; i++) {
+- reg = hub->vm_context0_cntl + i;
+- tmp = RREG32(reg);
+- tmp |= bits;
+- WREG32(reg, tmp);
+- }
+- break;
+ default:
+ break;
+ }
+--
+2.7.4
+