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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0889-drm-amd-amdgpu-Tidy-up-gfx_v9_0_enable_sck_slow_down.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0889-drm-amd-amdgpu-Tidy-up-gfx_v9_0_enable_sck_slow_down.patch41
1 files changed, 41 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0889-drm-amd-amdgpu-Tidy-up-gfx_v9_0_enable_sck_slow_down.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0889-drm-amd-amdgpu-Tidy-up-gfx_v9_0_enable_sck_slow_down.patch
new file mode 100644
index 00000000..af0cef7f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0889-drm-amd-amdgpu-Tidy-up-gfx_v9_0_enable_sck_slow_down.patch
@@ -0,0 +1,41 @@
+From 2ad3a6c9cd89ed11e282312a3dee55c56ba79c85 Mon Sep 17 00:00:00 2001
+From: Tom St Denis <tom.stdenis@amd.com>
+Date: Thu, 31 Aug 2017 09:02:33 -0400
+Subject: [PATCH 0889/4131] drm/amd/amdgpu: Tidy up
+ gfx_v9_0_enable_sck_slow_down_on_power_down()
+
+Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 15 +++++----------
+ 1 file changed, 5 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 81a3f55..d256107 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -1856,16 +1856,11 @@ static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *ad
+ uint32_t default_data = 0;
+
+ default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
+-
+- if (enable == true) {
+- data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
+- if(default_data != data)
+- WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
+- } else {
+- data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
+- if(default_data != data)
+- WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
+- }
++ data = REG_SET_FIELD(data, RLC_PG_CNTL,
++ SMU_CLK_SLOWDOWN_ON_PD_ENABLE,
++ enable ? 1 : 0);
++ if(default_data != data)
++ WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
+ }
+
+ static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev,
+--
+2.7.4
+