diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0742-drm-amd-display-use-some-sensible-time-out.patch')
-rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0742-drm-amd-display-use-some-sensible-time-out.patch | 298 |
1 files changed, 298 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0742-drm-amd-display-use-some-sensible-time-out.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0742-drm-amd-display-use-some-sensible-time-out.patch new file mode 100644 index 00000000..55b50f17 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0742-drm-amd-display-use-some-sensible-time-out.patch @@ -0,0 +1,298 @@ +From 4c9f4d6c771321698092e1074fe02d0fd3eb299f Mon Sep 17 00:00:00 2001 +From: Tony Cheng <tony.cheng@amd.com> +Date: Thu, 3 Aug 2017 21:23:04 -0400 +Subject: [PATCH 0742/4131] drm/amd/display: use some sensible time out + +40s time out is not sensible. + +also make all udelay poll happen more frequently since CPU is busy anyways + +Signed-off-by: Tony Cheng <tony.cheng@amd.com> +Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> +Acked-by: Harry Wentland <Harry.Wentland@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dc_helper.c | 6 ++++- + drivers/gpu/drm/amd/display/dc/dce/dce_abm.c | 11 +++++---- + drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 4 ++-- + .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 27 ++++++++++++++-------- + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 2 +- + .../amd/display/dc/dcn10/dcn10_timing_generator.c | 18 +++++++-------- + 6 files changed, 41 insertions(+), 27 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c +index f219bd2..0d84b2a 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc_helper.c ++++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c +@@ -135,6 +135,9 @@ uint32_t generic_reg_wait(const struct dc_context *ctx, + uint32_t reg_val; + int i; + ++ /* something is terribly wrong if time out is > 200ms. (5Hz) */ ++ ASSERT(delay_between_poll_us * time_out_num_tries <= 200000); ++ + if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { + /* 35 seconds */ + delay_between_poll_us = 35000; +@@ -158,7 +161,8 @@ uint32_t generic_reg_wait(const struct dc_context *ctx, + } + + dm_error("REG_WAIT timeout %dus * %d tries - %s line:%d\n", +- delay_between_poll_us, time_out_num_tries, func_name, line); ++ delay_between_poll_us, time_out_num_tries, ++ func_name, line); + + if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) + BREAK_TO_DEBUGGER(); +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c +index b4fa782..0e9d914 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c +@@ -195,8 +195,9 @@ static void driver_set_backlight_level(struct dce_abm *abm_dce, uint32_t level) + BL_PWM_GRP1_REG_LOCK, 0); + + /* 5.4.4 Wait for pending bit to be cleared */ +- REG_WAIT(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_REG_UPDATE_PENDING, +- 0, 10, 1000); ++ REG_WAIT(BL_PWM_GRP1_REG_LOCK, ++ BL_PWM_GRP1_REG_UPDATE_PENDING, 0, ++ 1, 10000); + } + + static void dmcu_set_backlight_level( +@@ -224,7 +225,7 @@ static void dmcu_set_backlight_level( + + /* waitDMCUReadyForCmd */ + REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, +- 0, 100, 800); ++ 0, 1, 80000); + + /* setDMCUParam_BL */ + REG_UPDATE(BL1_PWM_USER_LEVEL, BL1_PWM_USER_LEVEL, backlight_17_bit); +@@ -304,7 +305,7 @@ static bool dce_abm_set_level(struct abm *abm, uint32_t level) + struct dce_abm *abm_dce = TO_DCE_ABM(abm); + + REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, +- 100, 800); ++ 1, 80000); + + /* setDMCUParam_ABMLevel */ + REG_UPDATE_2(MASTER_COMM_CMD_REG, +@@ -322,7 +323,7 @@ static bool dce_abm_immediate_disable(struct abm *abm) + struct dce_abm *abm_dce = TO_DCE_ABM(abm); + + REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, +- 100, 800); ++ 1, 80000); + + /* setDMCUParam_ABMLevel */ + REG_UPDATE_2(MASTER_COMM_CMD_REG, +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c +index aaff946..92902f0 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c +@@ -262,7 +262,7 @@ static void dce_psr_wait_loop( + union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1; + + /* waitDMCUReadyForCmd */ +- REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 100); ++ REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); + + masterCmdData1.u32 = 0; + masterCmdData1.bits.wait_loop = wait_loop_number; +@@ -502,7 +502,7 @@ static void dcn10_psr_wait_loop( + union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1; + + /* waitDMCUReadyForCmd */ +- REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 100); ++ REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); + + masterCmdData1.u32 = 0; + masterCmdData1.bits.wait_loop = wait_loop_number; +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +index 9165dc8..292dfef 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +@@ -264,28 +264,32 @@ static void dpp_pg_control( + DOMAIN1_POWER_GATE, power_gate); + + REG_WAIT(DOMAIN1_PG_STATUS, +- DOMAIN1_PGFSM_PWR_STATUS, pwr_status, 20000, 200000); ++ DOMAIN1_PGFSM_PWR_STATUS, pwr_status, ++ 1, 1000); + break; + case 1: /* DPP1 */ + REG_UPDATE(DOMAIN3_PG_CONFIG, + DOMAIN3_POWER_GATE, power_gate); + + REG_WAIT(DOMAIN3_PG_STATUS, +- DOMAIN3_PGFSM_PWR_STATUS, pwr_status, 20000, 200000); ++ DOMAIN3_PGFSM_PWR_STATUS, pwr_status, ++ 1, 1000); + break; + case 2: /* DPP2 */ + REG_UPDATE(DOMAIN5_PG_CONFIG, + DOMAIN5_POWER_GATE, power_gate); + + REG_WAIT(DOMAIN5_PG_STATUS, +- DOMAIN5_PGFSM_PWR_STATUS, pwr_status, 20000, 200000); ++ DOMAIN5_PGFSM_PWR_STATUS, pwr_status, ++ 1, 1000); + break; + case 3: /* DPP3 */ + REG_UPDATE(DOMAIN7_PG_CONFIG, + DOMAIN7_POWER_GATE, power_gate); + + REG_WAIT(DOMAIN7_PG_STATUS, +- DOMAIN7_PGFSM_PWR_STATUS, pwr_status, 20000, 200000); ++ DOMAIN7_PGFSM_PWR_STATUS, pwr_status, ++ 1, 1000); + break; + default: + BREAK_TO_DEBUGGER(); +@@ -612,28 +616,32 @@ static void hubp_pg_control( + DOMAIN0_POWER_GATE, power_gate); + + REG_WAIT(DOMAIN0_PG_STATUS, +- DOMAIN0_PGFSM_PWR_STATUS, pwr_status, 20000, 200000); ++ DOMAIN0_PGFSM_PWR_STATUS, pwr_status, ++ 1, 1000); + break; + case 1: /* DCHUBP1 */ + REG_UPDATE(DOMAIN2_PG_CONFIG, + DOMAIN2_POWER_GATE, power_gate); + + REG_WAIT(DOMAIN2_PG_STATUS, +- DOMAIN2_PGFSM_PWR_STATUS, pwr_status, 20000, 200000); ++ DOMAIN2_PGFSM_PWR_STATUS, pwr_status, ++ 1, 1000); + break; + case 2: /* DCHUBP2 */ + REG_UPDATE(DOMAIN4_PG_CONFIG, + DOMAIN4_POWER_GATE, power_gate); + + REG_WAIT(DOMAIN4_PG_STATUS, +- DOMAIN4_PGFSM_PWR_STATUS, pwr_status, 20000, 200000); ++ DOMAIN4_PGFSM_PWR_STATUS, pwr_status, ++ 1, 1000); + break; + case 3: /* DCHUBP3 */ + REG_UPDATE(DOMAIN6_PG_CONFIG, + DOMAIN6_POWER_GATE, power_gate); + + REG_WAIT(DOMAIN6_PG_STATUS, +- DOMAIN6_PGFSM_PWR_STATUS, pwr_status, 20000, 200000); ++ DOMAIN6_PGFSM_PWR_STATUS, pwr_status, ++ 1, 1000); + break; + default: + BREAK_TO_DEBUGGER(); +@@ -1011,7 +1019,8 @@ static void reset_front_end( + + if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) + REG_WAIT(OTG_GLOBAL_SYNC_STATUS[tg->inst], +- VUPDATE_NO_LOCK_EVENT_OCCURRED, 1, 20000, 200000); ++ VUPDATE_NO_LOCK_EVENT_OCCURRED, 1, ++ 1, 100000); + + plane_atomic_disable(dc, fe_idx); + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c +index 036f161..52f2f2d 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c +@@ -72,7 +72,7 @@ static void mpc10_assert_idle_mpcc(struct mpc *mpc, int id) + ASSERT(!(mpc10->mpcc_in_use_mask & 1 << id)); + REG_WAIT(MPCC_STATUS[id], + MPCC_IDLE, 1, +- 1000, 1000); ++ 1, 100000); + } + + static int mpc10_get_idle_mpcc_id(struct dcn10_mpc *mpc10) +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c +index f4dce280..941e012 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c +@@ -312,7 +312,7 @@ static void tgn10_blank_crtc(struct timing_generator *tg) + */ + REG_WAIT(OTG_BLANK_CONTROL, + OTG_BLANK_DATA_EN, 1, +- 20000, 200000); ++ 1, 100000); + + REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL, + OTG_BLANK_DATA_DOUBLE_BUFFER_EN, 0); +@@ -351,7 +351,7 @@ static void tgn10_enable_optc_clock(struct timing_generator *tg, bool enable) + + REG_WAIT(OPTC_INPUT_CLOCK_CONTROL, + OPTC_INPUT_CLK_ON, 1, +- 2000, 500); ++ 1, 1000); + + /* Enable clock */ + REG_UPDATE_2(OTG_CLOCK_CONTROL, +@@ -359,7 +359,7 @@ static void tgn10_enable_optc_clock(struct timing_generator *tg, bool enable) + OTG_CLOCK_GATE_DIS, 1); + REG_WAIT(OTG_CLOCK_CONTROL, + OTG_CLOCK_ON, 1, +- 2000, 500); ++ 1, 1000); + } else { + REG_UPDATE_2(OTG_CLOCK_CONTROL, + OTG_CLOCK_GATE_DIS, 0, +@@ -368,7 +368,7 @@ static void tgn10_enable_optc_clock(struct timing_generator *tg, bool enable) + if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) + REG_WAIT(OTG_CLOCK_CONTROL, + OTG_CLOCK_ON, 0, +- 2000, 500); ++ 1, 1000); + + REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL, + OPTC_INPUT_CLK_GATE_DIS, 0, +@@ -377,7 +377,7 @@ static void tgn10_enable_optc_clock(struct timing_generator *tg, bool enable) + if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) + REG_WAIT(OPTC_INPUT_CLOCK_CONTROL, + OPTC_INPUT_CLK_ON, 0, +- 2000, 500); ++ 1, 1000); + } + } + +@@ -429,7 +429,7 @@ static bool tgn10_disable_crtc(struct timing_generator *tg) + /* CRTC disabled, so disable clock. */ + REG_WAIT(OTG_CLOCK_CONTROL, + OTG_BUSY, 0, +- 2000, 500); ++ 1, 100000); + + return true; + } +@@ -556,7 +556,7 @@ static void tgn10_unlock(struct timing_generator *tg) + /* why are we waiting here? */ + REG_WAIT(OTG_DOUBLE_BUFFER_CONTROL, + OTG_UPDATE_PENDING, 0, +- 20000, 200000); ++ 1, 100000); + } + + static void tgn10_get_position(struct timing_generator *tg, +@@ -651,13 +651,13 @@ static void tgn10_wait_for_state(struct timing_generator *tg, + case CRTC_STATE_VBLANK: + REG_WAIT(OTG_STATUS, + OTG_V_BLANK, 1, +- 100, 100000); /* 1 vupdate at 10hz */ ++ 1, 100000); /* 1 vupdate at 10hz */ + break; + + case CRTC_STATE_VACTIVE: + REG_WAIT(OTG_STATUS, + OTG_V_ACTIVE_DISP, 1, +- 100, 100000); /* 1 vupdate at 10hz */ ++ 1, 100000); /* 1 vupdate at 10hz */ + break; + + default: +-- +2.7.4 + |