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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0723-drm-amd-display-fix-PHYCLK-in-formula.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0723-drm-amd-display-fix-PHYCLK-in-formula.patch109
1 files changed, 109 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0723-drm-amd-display-fix-PHYCLK-in-formula.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0723-drm-amd-display-fix-PHYCLK-in-formula.patch
new file mode 100644
index 00000000..5a8e4492
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0723-drm-amd-display-fix-PHYCLK-in-formula.patch
@@ -0,0 +1,109 @@
+From 531cfcb26bd73a29a4510a2014c9e42cd10994b2 Mon Sep 17 00:00:00 2001
+From: Charlene Liu <charlene.liu@amd.com>
+Date: Mon, 31 Jul 2017 15:35:01 -0400
+Subject: [PATCH 0723/4131] drm/amd/display: fix PHYCLK in formula.
+
+Signed-off-by: Charlene Liu <charlene.liu@amd.com>
+Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Harry Wentland <Harry.Wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c | 11 +++++++++
+ drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 28 ++++++++++++----------
+ drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h | 5 ++++
+ 3 files changed, 32 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c
+index fb5d8db..e8086c0 100644
+--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c
++++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c
+@@ -266,6 +266,17 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v)
+ v->required_output_bw = v->pixel_clock[k] * 3.0;
+ }
+ if (v->output[k] == dcn_bw_hdmi) {
++ v->required_phyclk[k] = v->required_output_bw;
++ switch (v->output_deep_color[k]) {
++ case dcn_bw_encoder_10bpc:
++ v->required_phyclk[k] = v->required_phyclk[k] * 5.0 / 4;
++ break;
++ case dcn_bw_encoder_12bpc:
++ v->required_phyclk[k] = v->required_phyclk[k] * 3.0 / 2;
++ break;
++ default:
++ break;
++ }
+ v->required_phyclk[k] = v->required_output_bw / 3.0;
+ }
+ else if (v->output[k] == dcn_bw_dp) {
+diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+index 1922c13..13b7d887 100644
+--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
++++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+@@ -856,18 +856,6 @@ bool dcn_validate_bandwidth(
+ - pipe->stream->timing.v_front_porch;
+ v->vactive[input_idx] = pipe->stream->timing.v_addressable;
+ v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_khz / 1000.0f;
+- if (pipe->stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
+- switch (pipe->stream->timing.display_color_depth) {
+- case COLOR_DEPTH_101010:
+- v->pixel_clock[input_idx] = (v->pixel_clock[input_idx] * 30) / 24;
+- break;
+- case COLOR_DEPTH_121212:
+- v->pixel_clock[input_idx] = (v->pixel_clock[input_idx] * 36) / 24;
+- break;
+- default:
+- break;
+- }
+- }
+
+ if (!pipe->plane_state) {
+ v->dcc_enable[input_idx] = dcn_bw_yes;
+@@ -938,6 +926,22 @@ bool dcn_validate_bandwidth(
+ PIXEL_ENCODING_YCBCR420 ? dcn_bw_420 : dcn_bw_444;
+ v->output[input_idx] = pipe->stream->sink->sink_signal ==
+ SIGNAL_TYPE_HDMI_TYPE_A ? dcn_bw_hdmi : dcn_bw_dp;
++ v->output_deep_color[input_idx] = dcn_bw_encoder_8bpc;
++ if (v->output[input_idx] == dcn_bw_hdmi) {
++ switch (pipe->stream->timing.display_color_depth) {
++ case COLOR_DEPTH_101010:
++ v->output_deep_color[input_idx] = dcn_bw_encoder_10bpc;
++ break;
++ case COLOR_DEPTH_121212:
++ v->output_deep_color[input_idx] = dcn_bw_encoder_12bpc;
++ break;
++ case COLOR_DEPTH_161616:
++ v->output_deep_color[input_idx] = dcn_bw_encoder_16bpc;
++ break;
++ default:
++ break;
++ }
++ }
+
+ input_idx++;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
+index b6cc074..7e8abcd 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
+@@ -89,6 +89,10 @@ enum dcn_bw_defs {
+ dcn_bw_supported_in_v_blank,
+ dcn_bw_not_supported,
+ dcn_bw_na,
++ dcn_bw_encoder_8bpc,
++ dcn_bw_encoder_10bpc,
++ dcn_bw_encoder_12bpc,
++ dcn_bw_encoder_16bpc,
+ };
+
+ /*bounding box parameters*/
+@@ -182,6 +186,7 @@ struct dcn_bw_internal_vars {
+ enum dcn_bw_defs source_pixel_format[number_of_planes_minus_one + 1];
+ enum dcn_bw_defs source_surface_mode[number_of_planes_minus_one + 1];
+ enum dcn_bw_defs output_format[number_of_planes_minus_one + 1];
++ enum dcn_bw_defs output_deep_color[number_of_planes_minus_one + 1];
+ enum dcn_bw_defs output[number_of_planes_minus_one + 1];
+ float scaler_rec_out_width[number_of_planes_minus_one + 1];
+ float scaler_recout_height[number_of_planes_minus_one + 1];
+--
+2.7.4
+