diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0698-drm-amd-display-Initial-prototype-of-FBC-implementat.patch')
-rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0698-drm-amd-display-Initial-prototype-of-FBC-implementat.patch | 186 |
1 files changed, 186 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0698-drm-amd-display-Initial-prototype-of-FBC-implementat.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0698-drm-amd-display-Initial-prototype-of-FBC-implementat.patch new file mode 100644 index 00000000..5df47da0 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0698-drm-amd-display-Initial-prototype-of-FBC-implementat.patch @@ -0,0 +1,186 @@ +From 3b6a1c21a1de385d0151b0242c176469f1c1a715 Mon Sep 17 00:00:00 2001 +From: Roman Li <Roman.Li@amd.com> +Date: Thu, 27 Jul 2017 20:00:06 -0400 +Subject: [PATCH 0698/4131] drm/amd/display: Initial prototype of FBC + implementation + +- Protected by ENABLE_FBC compile flag + +Signed-off-by: Roman Li <Roman.Li@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Harry Wentland <Harry.Wentland@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/display/dc/core/dc.c | 7 ++- + drivers/gpu/drm/amd/display/dc/dc.h | 3 + + drivers/gpu/drm/amd/display/dc/dc_types.h | 3 + + .../amd/display/dc/dce110/dce110_hw_sequencer.c | 69 ++++++++++++++++++++++ + drivers/gpu/drm/amd/display/dc/inc/compressor.h | 1 + + 5 files changed, 81 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c +index df8c5ca..1c0d218 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c +@@ -475,7 +475,9 @@ static bool construct(struct core_dc *dc, + + dc_version = resource_parse_asic_id(init_params->asic_id); + dc->ctx->dce_version = dc_version; +- ++#ifdef ENABLE_FBC ++ dc->ctx->fbc_gpu_addr = init_params->fbc_gpu_addr; ++#endif + /* Resource should construct all asic specific resources. + * This should be the only place where we need to parse the asic id + */ +@@ -919,7 +921,7 @@ bool dc_enable_stereo( + #ifdef ENABLE_FBC + if (fbc_compressor != NULL && + fbc_compressor->funcs->is_fbc_enabled_in_hw(core_dc->fbc_compressor, +- &pipe->tg->inst)) ++ NULL)) + fbc_compressor->funcs->disable_fbc(fbc_compressor); + + #endif +@@ -2066,3 +2068,4 @@ void dc_log_hw_state(struct dc *dc) + if (core_dc->hwss.log_hw_state) + core_dc->hwss.log_hw_state(core_dc); + } ++ +diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h +index e9c9b91..63fd5b3 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc.h ++++ b/drivers/gpu/drm/amd/display/dc/dc.h +@@ -231,6 +231,9 @@ struct dc_init_data { + enum dce_environment dce_environment; + + struct dc_config flags; ++#ifdef ENABLE_FBC ++ uint64_t fbc_gpu_addr; ++#endif + }; + + struct dc *dc_create(const struct dc_init_data *init_params); +diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h +index 99b893f..ee9e6bc 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc_types.h ++++ b/drivers/gpu/drm/amd/display/dc/dc_types.h +@@ -92,6 +92,9 @@ struct dc_context { + bool created_bios; + struct gpio_service *gpio_service; + struct i2caux *i2caux; ++#ifdef ENABLE_FBC ++ uint64_t fbc_gpu_addr; ++#endif + }; + + +diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +index ad831e5..b62a761 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +@@ -1528,6 +1528,69 @@ static void apply_min_clocks( + } + } + ++#ifdef ENABLE_FBC ++ ++/* ++ * Check if FBC can be enabled ++ */ ++static enum dc_status validate_fbc(struct core_dc *dc, ++ struct validate_context *context) ++{ ++ struct pipe_ctx *pipe_ctx = ++ &context->res_ctx.pipe_ctx[0]; ++ ++ ASSERT(dc->fbc_compressor); ++ ++ /* FBC memory should be allocated */ ++ if (!dc->ctx->fbc_gpu_addr) ++ return DC_ERROR_UNEXPECTED; ++ ++ /* Only supports single display */ ++ if (context->stream_count != 1) ++ return DC_ERROR_UNEXPECTED; ++ ++ /* Only supports eDP */ ++ if (pipe_ctx->stream->sink->link->connector_signal != SIGNAL_TYPE_EDP) ++ return DC_ERROR_UNEXPECTED; ++ ++ /* PSR should not be enabled */ ++ if (pipe_ctx->stream->sink->link->psr_enabled) ++ return DC_ERROR_UNEXPECTED; ++ ++ return DC_OK; ++} ++ ++/* ++ * Enable FBC ++ */ ++static enum dc_status enable_fbc(struct core_dc *dc, ++ struct validate_context *context) ++{ ++ enum dc_status status = validate_fbc(dc, context); ++ ++ if (status == DC_OK) { ++ /* Program GRPH COMPRESSED ADDRESS and PITCH */ ++ struct compr_addr_and_pitch_params params = {0, 0, 0}; ++ struct compressor *compr = dc->fbc_compressor; ++ struct pipe_ctx *pipe_ctx = ++ &context->res_ctx.pipe_ctx[0]; ++ ++ params.source_view_width = ++ pipe_ctx->stream->timing.h_addressable; ++ params.source_view_height = ++ pipe_ctx->stream->timing.v_addressable; ++ ++ compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr; ++ ++ compr->funcs->surface_address_and_pitch(compr, ¶ms); ++ compr->funcs->set_fbc_invalidation_triggers(compr, 1); ++ ++ compr->funcs->enable_fbc(compr, ¶ms); ++ } ++ return status; ++} ++#endif ++ + static enum dc_status apply_ctx_to_hw_fpga( + struct core_dc *dc, + struct validate_context *context) +@@ -1836,6 +1899,11 @@ enum dc_status dce110_apply_ctx_to_hw( + + switch_dp_clock_sources(dc, &context->res_ctx); + ++#ifdef ENABLE_FBC ++ if (dc->fbc_compressor) ++ enable_fbc(dc, context); ++ ++#endif + + return DC_OK; + } +@@ -2244,6 +2312,7 @@ static void init_hw(struct core_dc *dc) + if (dc->fbc_compressor) + dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor); + #endif ++ + } + + void dce110_fill_display_configs( +diff --git a/drivers/gpu/drm/amd/display/dc/inc/compressor.h b/drivers/gpu/drm/amd/display/dc/inc/compressor.h +index 24cca18..bcb18f5 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/compressor.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/compressor.h +@@ -42,6 +42,7 @@ union fbc_physical_address { + uint32_t low_part; + int32_t high_part; + } addr; ++ uint64_t quad_part; + }; + + struct compr_addr_and_pitch_params { +-- +2.7.4 + |