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-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0678-drm-amd-display-log-HUBP-using-DTN-logging.patch344
1 files changed, 344 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0678-drm-amd-display-log-HUBP-using-DTN-logging.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0678-drm-amd-display-log-HUBP-using-DTN-logging.patch
new file mode 100644
index 00000000..fbd9b591
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0678-drm-amd-display-log-HUBP-using-DTN-logging.patch
@@ -0,0 +1,344 @@
+From e8e9d927c98ee7dcb736244a4c0dd8bc338c2fde Mon Sep 17 00:00:00 2001
+From: Tony Cheng <tony.cheng@amd.com>
+Date: Tue, 25 Jul 2017 22:52:45 -0400
+Subject: [PATCH 0678/4131] drm/amd/display: log HUBP using DTN logging
+
+also simplify DTN INFO. all we need is a way to have DC log register states
+some where we can compare with golden. going through connectivity is overkill.
+
+Signed-off-by: Tony Cheng <tony.cheng@amd.com>
+Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Acked-by: Harry Wentland <Harry.Wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 9 ++++
+ .../gpu/drm/amd/display/dc/basics/log_helpers.c | 28 ------------
+ drivers/gpu/drm/amd/display/dc/basics/logger.c | 3 +-
+ .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 53 +++++++++++++++++++---
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 34 ++++++++++++++
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h | 18 ++++++++
+ drivers/gpu/drm/amd/display/dc/dm_helpers.h | 6 ---
+ drivers/gpu/drm/amd/display/dc/dm_services.h | 12 +++++
+ .../gpu/drm/amd/display/include/logger_interface.h | 24 +++++-----
+ 9 files changed, 133 insertions(+), 54 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+index df4d221..6c19a07 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+@@ -327,6 +327,15 @@ bool dm_helpers_dc_conn_log(struct dc_context *ctx, struct log_entry *entry, enu
+ return true;
+ }
+
++void dm_dtn_log_begin(struct dc_context *ctx)
++{}
++
++void dm_dtn_log_append_v(struct dc_context *ctx,
++ const char *pMsg, ...)
++{}
++
++void dm_dtn_log_end(struct dc_context *ctx)
++{}
+
+ bool dm_helpers_dp_mst_start_top_mgr(
+ struct dc_context *ctx,
+diff --git a/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c b/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c
+index 070ae6f..785b943 100644
+--- a/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c
++++ b/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c
+@@ -100,31 +100,3 @@ void dc_conn_log(struct dc_context *ctx,
+
+ va_end(args);
+ }
+-
+-void dc_raw_log(struct dc_context *ctx,
+- enum dc_log_type event,
+- const char *msg,
+- ...)
+-{
+- va_list args;
+- struct log_entry entry = { 0 };
+-
+- dm_logger_open(ctx->logger, &entry, event);
+-
+- va_start(args, msg);
+- entry.buf_offset += dm_log_to_buffer(
+- &entry.buf[entry.buf_offset],
+- LOG_MAX_LINE_SIZE - entry.buf_offset,
+- msg, args);
+-
+- if (entry.buf[strlen(entry.buf) - 1] == '\n') {
+- entry.buf[strlen(entry.buf) - 1] = '\0';
+- entry.buf_offset--;
+- }
+-
+- dm_logger_append(&entry, "^\n");
+- dm_helpers_dc_conn_log(ctx, &entry, event);
+- dm_logger_close(&entry);
+-
+- va_end(args);
+-}
+diff --git a/drivers/gpu/drm/amd/display/dc/basics/logger.c b/drivers/gpu/drm/amd/display/dc/basics/logger.c
+index dfd2378..0b17374 100644
+--- a/drivers/gpu/drm/amd/display/dc/basics/logger.c
++++ b/drivers/gpu/drm/amd/display/dc/basics/logger.c
+@@ -428,8 +428,7 @@ void dm_logger_open(
+
+ logger->open_count++;
+
+- if (log_type != LOG_DTN)
+- log_heading(entry);
++ log_heading(entry);
+ }
+
+ void dm_logger_close(struct log_entry *entry)
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 03f4048..e738387 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -31,9 +31,9 @@
+ #include "dce110/dce110_hw_sequencer.h"
+ #include "dce/dce_hwseq.h"
+ #include "abm.h"
++#include "dcn10/dcn10_mem_input.h"
+ #include "dcn10/dcn10_dpp.h"
+ #include "dcn10/dcn10_mpc.h"
+-#include "mem_input.h"
+ #include "timing_generator.h"
+ #include "opp.h"
+ #include "ipp.h"
+@@ -2402,22 +2402,61 @@ static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct core_dc *dc)
+ return;
+ }
+
+-static void dcn10_log_hw_state(struct core_dc *dc)
++
++static void log_mpc_crc(struct core_dc *dc)
+ {
+ struct dc_context *dc_ctx = dc->ctx;
+ struct dce_hwseq *hws = dc->hwseq;
+
+- DTN_INFO("Hello World");
+-
+ if (REG(MPC_CRC_RESULT_GB))
+ DTN_INFO("MPC_CRC_RESULT_GB:%d MPC_CRC_RESULT_C:%d MPC_CRC_RESULT_AR:%d\n",
+ REG_READ(MPC_CRC_RESULT_GB), REG_READ(MPC_CRC_RESULT_C), REG_READ(MPC_CRC_RESULT_AR));
+ if (REG(DPP_TOP0_DPP_CRC_VAL_B_A))
+ DTN_INFO("DPP_TOP0_DPP_CRC_VAL_B_A:%d DPP_TOP0_DPP_CRC_VAL_R_G:%d\n",
+ REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G));
+- /* todo: add meaningful register reads and print out HW state
+- *
+- */
++}
++
++static void dcn10_log_hw_state(struct core_dc *dc)
++{
++ struct dc_context *dc_ctx = dc->ctx;
++ struct resource_pool *pool = dc->res_pool;
++ int i;
++
++ DTN_INFO_BEGIN();
++
++ DTN_INFO("HUBP:\t format \t addr_hi \t width \t height \t rotation \t"
++ "mirror \t sw_mode \t dcc_en \t blank_en \t ttu_dis \t"
++ "min_ttu_vblank \t qos_low_wm \t qos_high_wm \n");
++
++ for (i = 0; i < pool->pipe_count; i++) {
++ struct mem_input *mi = pool->mis[i];
++ struct dcn_hubp_state s;
++
++ dcn10_mem_input_read_state(TO_DCN10_MEM_INPUT(mi), &s);
++
++ DTN_INFO("[%d]:\t %xh \t %xh \t %d \t %d \t %xh \t %xh \t "
++ "%d \t %d \t %d \t %d \t"
++ "%d \t %d \t %d \n",
++ i,
++ s.pixel_format,
++ s.inuse_addr_hi,
++ s.viewport_width,
++ s.viewport_height,
++ s.rotation_angle,
++ s.h_mirror_en,
++ s.sw_mode,
++ s.dcc_en,
++ s.blank_en,
++ s.ttu_disable,
++ s.min_ttu_vblank,
++ s.qos_level_low_wm,
++ s.qos_level_high_wm);
++ }
++ DTN_INFO("\n");
++
++ log_mpc_crc(dc);
++
++ DTN_INFO_END();
+ }
+
+ static void dcn10_wait_for_mpcc_disconnect(
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
+index c56a69b..6f01db6 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
+@@ -804,6 +804,40 @@ static void min_set_viewport(
+ PRI_VIEWPORT_Y_START_C, viewport_c->y);
+ }
+
++void dcn10_mem_input_read_state(struct dcn10_mem_input *mi,
++ struct dcn_hubp_state *s)
++{
++ REG_GET(DCSURF_SURFACE_CONFIG,
++ SURFACE_PIXEL_FORMAT, &s->pixel_format);
++
++ REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,
++ SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi);
++
++ REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION,
++ PRI_VIEWPORT_WIDTH, &s->viewport_width,
++ PRI_VIEWPORT_HEIGHT, &s->viewport_height);
++
++ REG_GET_2(DCSURF_SURFACE_CONFIG,
++ ROTATION_ANGLE, &s->rotation_angle,
++ H_MIRROR_EN, &s->h_mirror_en);
++
++ REG_GET(DCSURF_TILING_CONFIG,
++ SW_MODE, &s->sw_mode);
++
++ REG_GET(DCSURF_SURFACE_CONTROL,
++ PRIMARY_SURFACE_DCC_EN, &s->dcc_en);
++
++ REG_GET_2(DCHUBP_CNTL,
++ HUBP_BLANK_EN, &s->blank_en,
++ HUBP_TTU_DISABLE, &s->ttu_disable);
++
++ REG_GET(DCN_GLOBAL_TTU_CNTL,
++ MIN_TTU_VBLANK, &s->min_ttu_vblank);
++
++ REG_GET_2(DCN_TTU_QOS_WM,
++ QoS_LEVEL_LOW_WM, &s->qos_level_low_wm,
++ QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm);
++}
+
+ static struct mem_input_funcs dcn10_mem_input_funcs = {
+ .mem_input_program_display_marks = min10_program_display_marks,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
+index 9130f5e..4f4e2c0 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
+@@ -579,4 +579,22 @@ bool dcn10_mem_input_construct(
+ const struct dcn_mi_shift *mi_shift,
+ const struct dcn_mi_mask *mi_mask);
+
++struct dcn_hubp_state {
++ uint32_t pixel_format;
++ uint32_t inuse_addr_hi;
++ uint32_t viewport_width;
++ uint32_t viewport_height;
++ uint32_t rotation_angle;
++ uint32_t h_mirror_en;
++ uint32_t sw_mode;
++ uint32_t dcc_en;
++ uint32_t blank_en;
++ uint32_t ttu_disable;
++ uint32_t min_ttu_vblank;
++ uint32_t qos_level_low_wm;
++ uint32_t qos_level_high_wm;
++};
++void dcn10_mem_input_read_state(struct dcn10_mem_input *mi,
++ struct dcn_hubp_state *s);
++
+ #endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dm_helpers.h b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
+index a831421..e8bd501 100644
+--- a/drivers/gpu/drm/amd/display/dc/dm_helpers.h
++++ b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
+@@ -68,15 +68,9 @@ bool dm_helpers_dp_mst_start_top_mgr(
+ const struct dc_link *link,
+ bool boot);
+
+-bool dm_helpers_dc_conn_log(
+- struct dc_context*ctx,
+- struct log_entry *entry,
+- enum dc_log_type event);
+-
+ void dm_helpers_dp_mst_stop_top_mgr(
+ struct dc_context *ctx,
+ const struct dc_link *link);
+-
+ /**
+ * OS specific aux read callback.
+ */
+diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h
+index ea494a7..e9bf4c4 100644
+--- a/drivers/gpu/drm/amd/display/dc/dm_services.h
++++ b/drivers/gpu/drm/amd/display/dc/dm_services.h
+@@ -463,4 +463,16 @@ bool dm_dmcu_set_pipe(struct dc_context *ctx, unsigned int controller_id);
+ #define dm_log_to_buffer(buffer, size, fmt, args)\
+ vsnprintf(buffer, size, fmt, args)
+
++/*
++ * Debug and verification hooks
++ */
++bool dm_helpers_dc_conn_log(
++ struct dc_context *ctx,
++ struct log_entry *entry,
++ enum dc_log_type event);
++
++void dm_dtn_log_begin(struct dc_context *ctx);
++void dm_dtn_log_append_v(struct dc_context *ctx, const char *msg, ...);
++void dm_dtn_log_end(struct dc_context *ctx);
++
+ #endif /* __DM_SERVICES_H__ */
+diff --git a/drivers/gpu/drm/amd/display/include/logger_interface.h b/drivers/gpu/drm/amd/display/include/logger_interface.h
+index 3adf3cf..0a87247 100644
+--- a/drivers/gpu/drm/amd/display/include/logger_interface.h
++++ b/drivers/gpu/drm/amd/display/include/logger_interface.h
+@@ -70,11 +70,6 @@ void dc_conn_log(struct dc_context *ctx,
+ const char *msg,
+ ...);
+
+-void dc_raw_log(struct dc_context *ctx,
+- enum dc_log_type event,
+- const char *msg,
+- ...);
+-
+ void logger_write(struct dal_logger *logger,
+ enum dc_log_type log_type,
+ const char *msg,
+@@ -121,16 +116,11 @@ void context_clock_trace(
+
+ #define DC_ERROR(...) \
+ dm_logger_write(dc_ctx->logger, LOG_ERROR, \
+- __VA_ARGS__);
+-
+-#define DTN_INFO(...) \
+- dc_raw_log(dc_ctx, LOG_DTN, \
+ __VA_ARGS__)
+
+ #define DC_SYNC_INFO(...) \
+ dm_logger_write(dc_ctx->logger, LOG_SYNC, \
+- __VA_ARGS__);
+-
++ __VA_ARGS__)
+
+ /* Connectivity log format:
+ * [time stamp] [drm] [Major_minor] [connector name] message.....
+@@ -155,4 +145,16 @@ void context_clock_trace(
+ dc_conn_log(link->ctx, link, NULL, 0, \
+ LOG_EVENT_MODE_SET, ##__VA_ARGS__)
+
++/*
++ * Display Test Next logging
++ */
++#define DTN_INFO_BEGIN() \
++ dm_dtn_log_begin(dc_ctx)
++
++#define DTN_INFO(msg, ...) \
++ dm_dtn_log_append_v(dc_ctx, msg, ##__VA_ARGS__)
++
++#define DTN_INFO_END() \
++ dm_dtn_log_end(dc_ctx)
++
+ #endif /* __DAL_LOGGER_INTERFACE_H__ */
+--
+2.7.4
+