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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0657-drm-amd-display-Move-DCHUBBUB-block-from-MemInput-to.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0657-drm-amd-display-Move-DCHUBBUB-block-from-MemInput-to.patch1260
1 files changed, 1260 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0657-drm-amd-display-Move-DCHUBBUB-block-from-MemInput-to.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0657-drm-amd-display-Move-DCHUBBUB-block-from-MemInput-to.patch
new file mode 100644
index 00000000..c77cc39a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0657-drm-amd-display-Move-DCHUBBUB-block-from-MemInput-to.patch
@@ -0,0 +1,1260 @@
+From e4f1ded963c5f7c214787e60df4a579448d96701 Mon Sep 17 00:00:00 2001
+From: Zeyu Fan <Zeyu.Fan@amd.com>
+Date: Sun, 23 Jul 2017 18:30:15 -0400
+Subject: [PATCH 0657/4131] drm/amd/display: Move DCHUBBUB block from MemInput
+ to HW sequencer.
+
+Signed-off-by: Zeyu Fan <Zeyu.Fan@amd.com>
+Reviewed-by: Zeyu Fan <Zeyu.Fan@amd.com>
+Acked-by: Harry Wentland <Harry.Wentland@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 6 +-
+ drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 116 +++++++-
+ drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 54 +---
+ .../amd/display/dc/dce110/dce110_hw_sequencer.c | 1 +
+ .../amd/display/dc/dce120/dce120_hw_sequencer.c | 64 +++++
+ .../drm/amd/display/dc/dce120/dce120_resource.c | 2 +-
+ .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 304 ++++++++++++++++++++-
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 303 --------------------
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h | 76 +-----
+ drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 7 +-
+ drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 4 +
+ 11 files changed, 492 insertions(+), 445 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 9ef6717..e89a2e5 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -2042,10 +2042,10 @@ bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data)
+ return false;
+ }
+
+- if (mi->funcs->mem_input_update_dchub)
+- mi->funcs->mem_input_update_dchub(mi, dh_data);
++ if (core_dc->hwss.update_dchub)
++ core_dc->hwss.update_dchub(core_dc->hwseq, dh_data);
+ else
+- ASSERT(mi->funcs->mem_input_update_dchub);
++ ASSERT(core_dc->hwss.update_dchub);
+
+
+ return true;
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+index 7feb1ca..a8a5569 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+@@ -116,6 +116,15 @@
+ .BLND_V_UPDATE_LOCK[3] = mmBLNDV_V_UPDATE_LOCK, \
+ .BLND_CONTROL[3] = mmBLNDV_CONTROL
+
++#define HWSEQ_DCE120_REG_LIST() \
++ HWSEQ_DCE10_REG_LIST(), \
++ HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \
++ HWSEQ_PHYPLL_REG_LIST(CRTC), \
++ SR(DCHUB_FB_LOCATION),\
++ SR(DCHUB_AGP_BASE),\
++ SR(DCHUB_AGP_BOT),\
++ SR(DCHUB_AGP_TOP)
++
+ #define HWSEQ_DCE112_REG_LIST() \
+ HWSEQ_DCE10_REG_LIST(), \
+ HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \
+@@ -146,8 +155,31 @@
+ SRII(OPP_PIPE_CONTROL, OPP_PIPE, 2), \
+ SRII(OPP_PIPE_CONTROL, OPP_PIPE, 3), \
+ SR(REFCLK_CNTL), \
++ SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\
++ SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A),\
++ SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A),\
++ SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A),\
++ SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A),\
++ SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\
++ SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B),\
++ SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B),\
++ SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B),\
++ SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B),\
++ SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\
++ SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C),\
++ SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C),\
++ SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C),\
++ SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C),\
++ SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\
++ SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D),\
++ SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D),\
++ SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D),\
++ SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D),\
++ SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\
++ SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\
++ SR(DCHUBBUB_ARB_SAT_LEVEL),\
++ SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\
+ SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
+- SR(DCHUBBUB_ARB_DRAM_STATE_CNTL), \
+ SR(DCHUBBUB_TEST_DEBUG_INDEX), \
+ SR(DCHUBBUB_TEST_DEBUG_DATA), \
+ SR(DC_IP_REQUEST_CNTL), \
+@@ -180,7 +212,13 @@
+
+ #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ #define HWSEQ_DCN1_REG_LIST()\
+- HWSEQ_DCN_REG_LIST()
++ HWSEQ_DCN_REG_LIST(), \
++ SR(DCHUBBUB_SDPIF_FB_TOP),\
++ SR(DCHUBBUB_SDPIF_FB_BASE),\
++ SR(DCHUBBUB_SDPIF_FB_OFFSET),\
++ SR(DCHUBBUB_SDPIF_AGP_BASE),\
++ SR(DCHUBBUB_SDPIF_AGP_BOT),\
++ SR(DCHUBBUB_SDPIF_AGP_TOP)
+ #endif
+
+
+@@ -194,6 +232,11 @@ struct dce_hwseq_registers {
+ uint32_t CRTC_H_BLANK_START_END[6];
+ uint32_t PIXEL_RATE_CNTL[6];
+ uint32_t PHYPLL_PIXEL_RATE_CNTL[6];
++ /*DCHUB*/
++ uint32_t DCHUB_FB_LOCATION;
++ uint32_t DCHUB_AGP_BASE;
++ uint32_t DCHUB_AGP_BOT;
++ uint32_t DCHUB_AGP_TOP;
+
+ #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ uint32_t OTG_GLOBAL_SYNC_STATUS[4];
+@@ -202,10 +245,39 @@ struct dce_hwseq_registers {
+ uint32_t DPP_CONTROL[4];
+ uint32_t OPP_PIPE_CONTROL[4];
+ uint32_t REFCLK_CNTL;
++ uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A;
++ uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A;
++ uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A;
++ uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A;
++ uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;
++ uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B;
++ uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B;
++ uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B;
++ uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B;
++ uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;
++ uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C;
++ uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C;
++ uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C;
++ uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C;
++ uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;
++ uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D;
++ uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D;
++ uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D;
++ uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D;
++ uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;
++ uint32_t DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL;
++ uint32_t DCHUBBUB_ARB_SAT_LEVEL;
++ uint32_t DCHUBBUB_ARB_DF_REQ_OUTSTAND;
+ uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL;
+ uint32_t DCHUBBUB_ARB_DRAM_STATE_CNTL;
+ uint32_t DCHUBBUB_TEST_DEBUG_INDEX;
+ uint32_t DCHUBBUB_TEST_DEBUG_DATA;
++ uint32_t DCHUBBUB_SDPIF_FB_TOP;
++ uint32_t DCHUBBUB_SDPIF_FB_BASE;
++ uint32_t DCHUBBUB_SDPIF_FB_OFFSET;
++ uint32_t DCHUBBUB_SDPIF_AGP_BASE;
++ uint32_t DCHUBBUB_SDPIF_AGP_BOT;
++ uint32_t DCHUBBUB_SDPIF_AGP_TOP;
+ uint32_t DC_IP_REQUEST_CNTL;
+ uint32_t DOMAIN0_PG_CONFIG;
+ uint32_t DOMAIN1_PG_CONFIG;
+@@ -300,11 +372,19 @@ struct dce_hwseq_registers {
+ HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\
+ HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_)
+
++#define HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\
++ SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\
++ SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\
++ SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\
++ SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\
++ SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh)
++
+ #define HWSEQ_DCE12_MASK_SH_LIST(mask_sh)\
+ HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE0_DCFE_),\
+ HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND0_BLND_),\
+ HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\
+- HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_)
++ HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_),\
++ HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh)
+
+ #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ #define HWSEQ_DCN_MASK_SH_LIST(mask_sh)\
+@@ -342,6 +422,12 @@ struct dce_hwseq_registers {
+ HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \
+ HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \
+ HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
++ HWS_SF(, DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh), \
++ HWS_SF(, DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh), \
++ HWS_SF(, DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, mask_sh), \
++ HWS_SF(, DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, mask_sh), \
++ HWS_SF(, DCHUBBUB_ARB_SAT_LEVEL, DCHUBBUB_ARB_SAT_LEVEL, mask_sh), \
++ HWS_SF(, DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh), \
+ HWS_SF(, DCFCLK_CNTL, DCFCLK_GATE_DIS, mask_sh)
+ #endif
+
+@@ -349,6 +435,12 @@ struct dce_hwseq_registers {
+ #define HWSEQ_DCN1_MASK_SH_LIST(mask_sh)\
+ HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
+ HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh), \
++ HWS_SF(, DCHUBBUB_SDPIF_FB_TOP, SDPIF_FB_TOP, mask_sh), \
++ HWS_SF(, DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh), \
++ HWS_SF(, DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh), \
++ HWS_SF(, DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh), \
++ HWS_SF(, DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh), \
++ HWS_SF(, DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh), \
+ HWS_SF(DPP_TOP0_, DPP_CONTROL, DPPCLK_RATE_CONTROL, mask_sh)
+ #endif
+
+@@ -378,7 +470,25 @@ struct dce_hwseq_registers {
+ type HUBP_CLOCK_ENABLE; \
+ type DPP_CLOCK_ENABLE; \
+ type DPPCLK_RATE_CONTROL; \
++ type SDPIF_FB_TOP;\
++ type SDPIF_FB_BASE;\
++ type SDPIF_FB_OFFSET;\
++ type SDPIF_AGP_BASE;\
++ type SDPIF_AGP_BOT;\
++ type SDPIF_AGP_TOP;\
++ type FB_TOP;\
++ type FB_BASE;\
++ type FB_OFFSET;\
++ type AGP_BASE;\
++ type AGP_BOT;\
++ type AGP_TOP;\
+ type DCHUBBUB_GLOBAL_TIMER_ENABLE; \
++ type DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST;\
++ type DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE;\
++ type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE;\
++ type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE;\
++ type DCHUBBUB_ARB_SAT_LEVEL;\
++ type DCHUBBUB_ARB_MIN_REQ_OUTSTAND;\
+ type OPP_PIPE_CLOCK_EN;\
+ type IP_REQUEST_EN; \
+ type DOMAIN0_POWER_FORCEON; \
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
+index 157f4e1..6276697 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
+@@ -656,57 +656,6 @@ static bool dce_mi_program_surface_flip_and_addr(
+ return true;
+ }
+
+-static void dce_mi_update_dchub(struct mem_input *mi,
+- struct dchub_init_data *dh_data)
+-{
+- struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi);
+- /* TODO: port code from dal2 */
+- switch (dh_data->fb_mode) {
+- case FRAME_BUFFER_MODE_ZFB_ONLY:
+- /*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/
+- REG_UPDATE_2(DCHUB_FB_LOCATION,
+- FB_TOP, 0,
+- FB_BASE, 0x0FFFF);
+-
+- REG_UPDATE(DCHUB_AGP_BASE,
+- AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
+-
+- REG_UPDATE(DCHUB_AGP_BOT,
+- AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
+-
+- REG_UPDATE(DCHUB_AGP_TOP,
+- AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22);
+- break;
+- case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL:
+- /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
+- REG_UPDATE(DCHUB_AGP_BASE,
+- AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
+-
+- REG_UPDATE(DCHUB_AGP_BOT,
+- AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
+-
+- REG_UPDATE(DCHUB_AGP_TOP,
+- AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22);
+- break;
+- case FRAME_BUFFER_MODE_LOCAL_ONLY:
+- /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
+- REG_UPDATE(DCHUB_AGP_BASE,
+- AGP_BASE, 0);
+-
+- REG_UPDATE(DCHUB_AGP_BOT,
+- AGP_BOT, 0x03FFFF);
+-
+- REG_UPDATE(DCHUB_AGP_TOP,
+- AGP_TOP, 0);
+- break;
+- default:
+- break;
+- }
+-
+- dh_data->dchub_initialzied = true;
+- dh_data->dchub_info_valid = false;
+-}
+-
+ static struct mem_input_funcs dce_mi_funcs = {
+ .mem_input_program_display_marks = dce_mi_program_display_marks,
+ .allocate_mem_input = dce_mi_allocate_dmif,
+@@ -716,8 +665,7 @@ static struct mem_input_funcs dce_mi_funcs = {
+ .mem_input_program_pte_vm = dce_mi_program_pte_vm,
+ .mem_input_program_surface_config =
+ dce_mi_program_surface_config,
+- .mem_input_is_flip_pending = dce_mi_is_flip_pending,
+- .mem_input_update_dchub = dce_mi_update_dchub
++ .mem_input_is_flip_pending = dce_mi_is_flip_pending
+ };
+
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+index 6ab9712..efba8d7 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+@@ -49,6 +49,7 @@
+ #include "abm.h"
+ #include "audio.h"
+ #include "dce/dce_hwseq.h"
++#include "reg_helper.h"
+
+ /* include DCE11 register header files */
+ #include "dce/dce_11_0_d.h"
+diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
+index f5ffd8f6..91301b4 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
+@@ -28,6 +28,7 @@
+ #include "core_dc.h"
+ #include "core_types.h"
+ #include "dce120_hw_sequencer.h"
++#include "dce/dce_hwseq.h"
+
+ #include "dce110/dce110_hw_sequencer.h"
+
+@@ -37,6 +38,15 @@
+ #include "vega10/soc15ip.h"
+ #include "reg_helper.h"
+
++#define CTX \
++ hws->ctx
++#define REG(reg)\
++ hws->regs->reg
++
++#undef FN
++#define FN(reg_name, field_name) \
++ hws->shifts->field_name, hws->masks->field_name
++
+ struct dce120_hw_seq_reg_offsets {
+ uint32_t crtc;
+ };
+@@ -184,6 +194,59 @@ static bool dce120_enable_display_power_gating(
+ return false;
+ }
+
++static void dce120_update_dchub(
++ struct dce_hwseq *hws,
++ struct dchub_init_data *dh_data)
++{
++ /* TODO: port code from dal2 */
++ switch (dh_data->fb_mode) {
++ case FRAME_BUFFER_MODE_ZFB_ONLY:
++ /*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/
++ REG_UPDATE_2(DCHUB_FB_LOCATION,
++ FB_TOP, 0,
++ FB_BASE, 0x0FFFF);
++
++ REG_UPDATE(DCHUB_AGP_BASE,
++ AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
++
++ REG_UPDATE(DCHUB_AGP_BOT,
++ AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
++
++ REG_UPDATE(DCHUB_AGP_TOP,
++ AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22);
++ break;
++ case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL:
++ /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
++ REG_UPDATE(DCHUB_AGP_BASE,
++ AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
++
++ REG_UPDATE(DCHUB_AGP_BOT,
++ AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
++
++ REG_UPDATE(DCHUB_AGP_TOP,
++ AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22);
++ break;
++ case FRAME_BUFFER_MODE_LOCAL_ONLY:
++ /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
++ REG_UPDATE(DCHUB_AGP_BASE,
++ AGP_BASE, 0);
++
++ REG_UPDATE(DCHUB_AGP_BOT,
++ AGP_BOT, 0x03FFFF);
++
++ REG_UPDATE(DCHUB_AGP_TOP,
++ AGP_TOP, 0);
++ break;
++ default:
++ break;
++ }
++
++ dh_data->dchub_initialzied = true;
++ dh_data->dchub_info_valid = false;
++}
++
++
++
+ bool dce120_hw_sequencer_construct(struct core_dc *dc)
+ {
+ /* All registers used by dce11.2 match those in dce11 in offset and
+@@ -191,6 +254,7 @@ bool dce120_hw_sequencer_construct(struct core_dc *dc)
+ */
+ dce110_hw_sequencer_construct(dc);
+ dc->hwss.enable_display_power_gating = dce120_enable_display_power_gating;
++ dc->hwss.update_dchub = dce120_update_dchub;
+
+ return true;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+index 8248124..f829b6e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+@@ -598,7 +598,7 @@ static struct stream_encoder *dce120_stream_encoder_create(
+ mm ## block ## id ## _ ## reg_name
+
+ static const struct dce_hwseq_registers hwseq_reg = {
+- HWSEQ_DCE112_REG_LIST()
++ HWSEQ_DCE120_REG_LIST()
+ };
+
+ static const struct dce_hwseq_shift hwseq_shift = {
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index d61b63d..b794087 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -218,6 +218,306 @@ static void dpp_pg_control(
+ }
+ }
+
++static uint32_t convert_and_clamp(
++ uint32_t wm_ns,
++ uint32_t refclk_mhz,
++ uint32_t clamp_value)
++{
++ uint32_t ret_val = 0;
++ ret_val = wm_ns * refclk_mhz;
++ ret_val /= 1000;
++
++ if (ret_val > clamp_value)
++ ret_val = clamp_value;
++
++ return ret_val;
++}
++
++static void program_watermarks(
++ struct dce_hwseq *hws,
++ struct dcn_watermark_set *watermarks,
++ unsigned int refclk_mhz)
++{
++ uint32_t force_en = hws->ctx->dc->debug.disable_stutter ? 1 : 0;
++ /*
++ * Need to clamp to max of the register values (i.e. no wrap)
++ * for dcn1, all wm registers are 21-bit wide
++ */
++ uint32_t prog_wm_value;
++
++ /* Repeat for water mark set A, B, C and D. */
++ /* clock state A */
++ prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns,
++ refclk_mhz, 0x1fffff);
++ REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value);
++
++ dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
++ "URGENCY_WATERMARK_A calculated =%d\n"
++ "HW register value = 0x%x\n",
++ watermarks->a.urgent_ns, prog_wm_value);
++
++ prog_wm_value = convert_and_clamp(watermarks->a.pte_meta_urgent_ns,
++ refclk_mhz, 0x1fffff);
++ REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A, prog_wm_value);
++ dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
++ "PTE_META_URGENCY_WATERMARK_A calculated =%d\n"
++ "HW register value = 0x%x\n",
++ watermarks->a.pte_meta_urgent_ns, prog_wm_value);
++
++
++ prog_wm_value = convert_and_clamp(
++ watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns,
++ refclk_mhz, 0x1fffff);
++
++ REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value);
++ dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
++ "SR_ENTER_EXIT_WATERMARK_A calculated =%d\n"
++ "HW register value = 0x%x\n",
++ watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
++
++
++ prog_wm_value = convert_and_clamp(
++ watermarks->a.cstate_pstate.cstate_exit_ns,
++ refclk_mhz, 0x1fffff);
++ REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value);
++ dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
++ "SR_EXIT_WATERMARK_A calculated =%d\n"
++ "HW register value = 0x%x\n",
++ watermarks->a.cstate_pstate.cstate_exit_ns, prog_wm_value);
++
++
++ prog_wm_value = convert_and_clamp(
++ watermarks->a.cstate_pstate.pstate_change_ns,
++ refclk_mhz, 0x1fffff);
++ REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value);
++ dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
++ "DRAM_CLK_CHANGE_WATERMARK_A calculated =%d\n"
++ "HW register value = 0x%x\n\n",
++ watermarks->a.cstate_pstate.pstate_change_ns, prog_wm_value);
++
++
++ /* clock state B */
++ prog_wm_value = convert_and_clamp(
++ watermarks->b.urgent_ns, refclk_mhz, 0x1fffff);
++ REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, prog_wm_value);
++ dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
++ "URGENCY_WATERMARK_B calculated =%d\n"
++ "HW register value = 0x%x\n",
++ watermarks->b.urgent_ns, prog_wm_value);
++
++
++ prog_wm_value = convert_and_clamp(
++ watermarks->b.pte_meta_urgent_ns,
++ refclk_mhz, 0x1fffff);
++ REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B, prog_wm_value);
++ dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
++ "PTE_META_URGENCY_WATERMARK_B calculated =%d\n"
++ "HW register value = 0x%x\n",
++ watermarks->b.pte_meta_urgent_ns, prog_wm_value);
++
++
++ prog_wm_value = convert_and_clamp(
++ watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns,
++ refclk_mhz, 0x1fffff);
++ REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value);
++ dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
++ "SR_ENTER_WATERMARK_B calculated =%d\n"
++ "HW register value = 0x%x\n",
++ watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
++
++
++ prog_wm_value = convert_and_clamp(
++ watermarks->b.cstate_pstate.cstate_exit_ns,
++ refclk_mhz, 0x1fffff);
++ REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, prog_wm_value);
++ dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
++ "SR_EXIT_WATERMARK_B calculated =%d\n"
++ "HW register value = 0x%x\n",
++ watermarks->b.cstate_pstate.cstate_exit_ns, prog_wm_value);
++
++ prog_wm_value = convert_and_clamp(
++ watermarks->b.cstate_pstate.pstate_change_ns,
++ refclk_mhz, 0x1fffff);
++ REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value);
++ dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
++ "DRAM_CLK_CHANGE_WATERMARK_B calculated =%d\n\n"
++ "HW register value = 0x%x\n",
++ watermarks->b.cstate_pstate.pstate_change_ns, prog_wm_value);
++
++ /* clock state C */
++ prog_wm_value = convert_and_clamp(
++ watermarks->c.urgent_ns, refclk_mhz, 0x1fffff);
++ REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, prog_wm_value);
++ dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
++ "URGENCY_WATERMARK_C calculated =%d\n"
++ "HW register value = 0x%x\n",
++ watermarks->c.urgent_ns, prog_wm_value);
++
++
++ prog_wm_value = convert_and_clamp(
++ watermarks->c.pte_meta_urgent_ns,
++ refclk_mhz, 0x1fffff);
++ REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C, prog_wm_value);
++ dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
++ "PTE_META_URGENCY_WATERMARK_C calculated =%d\n"
++ "HW register value = 0x%x\n",
++ watermarks->c.pte_meta_urgent_ns, prog_wm_value);
++
++
++ prog_wm_value = convert_and_clamp(
++ watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns,
++ refclk_mhz, 0x1fffff);
++ REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value);
++ dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
++ "SR_ENTER_WATERMARK_C calculated =%d\n"
++ "HW register value = 0x%x\n",
++ watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
++
++
++ prog_wm_value = convert_and_clamp(
++ watermarks->c.cstate_pstate.cstate_exit_ns,
++ refclk_mhz, 0x1fffff);
++ REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, prog_wm_value);
++ dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
++ "SR_EXIT_WATERMARK_C calculated =%d\n"
++ "HW register value = 0x%x\n",
++ watermarks->c.cstate_pstate.cstate_exit_ns, prog_wm_value);
++
++
++ prog_wm_value = convert_and_clamp(
++ watermarks->c.cstate_pstate.pstate_change_ns,
++ refclk_mhz, 0x1fffff);
++ REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value);
++ dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
++ "DRAM_CLK_CHANGE_WATERMARK_C calculated =%d\n\n"
++ "HW register value = 0x%x\n",
++ watermarks->c.cstate_pstate.pstate_change_ns, prog_wm_value);
++
++ /* clock state D */
++ prog_wm_value = convert_and_clamp(
++ watermarks->d.urgent_ns, refclk_mhz, 0x1fffff);
++ REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, prog_wm_value);
++ dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
++ "URGENCY_WATERMARK_D calculated =%d\n"
++ "HW register value = 0x%x\n",
++ watermarks->d.urgent_ns, prog_wm_value);
++
++ prog_wm_value = convert_and_clamp(
++ watermarks->d.pte_meta_urgent_ns,
++ refclk_mhz, 0x1fffff);
++ REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D, prog_wm_value);
++ dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
++ "PTE_META_URGENCY_WATERMARK_D calculated =%d\n"
++ "HW register value = 0x%x\n",
++ watermarks->d.pte_meta_urgent_ns, prog_wm_value);
++
++
++ prog_wm_value = convert_and_clamp(
++ watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns,
++ refclk_mhz, 0x1fffff);
++ REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value);
++ dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
++ "SR_ENTER_WATERMARK_D calculated =%d\n"
++ "HW register value = 0x%x\n",
++ watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
++
++
++ prog_wm_value = convert_and_clamp(
++ watermarks->d.cstate_pstate.cstate_exit_ns,
++ refclk_mhz, 0x1fffff);
++ REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, prog_wm_value);
++ dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
++ "SR_EXIT_WATERMARK_D calculated =%d\n"
++ "HW register value = 0x%x\n",
++ watermarks->d.cstate_pstate.cstate_exit_ns, prog_wm_value);
++
++
++ prog_wm_value = convert_and_clamp(
++ watermarks->d.cstate_pstate.pstate_change_ns,
++ refclk_mhz, 0x1fffff);
++ REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value);
++ dm_logger_write(hws->ctx->logger, LOG_HW_MARKS,
++ "DRAM_CLK_CHANGE_WATERMARK_D calculated =%d\n"
++ "HW register value = 0x%x\n\n",
++ watermarks->d.cstate_pstate.pstate_change_ns, prog_wm_value);
++
++ REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
++ DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1);
++ REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
++ DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 0);
++ REG_UPDATE(DCHUBBUB_ARB_SAT_LEVEL,
++ DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz);
++ REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,
++ DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 68);
++
++ REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL,
++ DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, 0,
++ DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, force_en);
++
++#if 0
++ REG_UPDATE_2(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
++ DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, 1,
++ DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1);
++#endif
++}
++
++
++static void dcn10_update_dchub(
++ struct dce_hwseq *hws,
++ struct dchub_init_data *dh_data)
++{
++ /* TODO: port code from dal2 */
++ switch (dh_data->fb_mode) {
++ case FRAME_BUFFER_MODE_ZFB_ONLY:
++ /*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/
++ REG_UPDATE(DCHUBBUB_SDPIF_FB_TOP,
++ SDPIF_FB_TOP, 0);
++
++ REG_UPDATE(DCHUBBUB_SDPIF_FB_BASE,
++ SDPIF_FB_BASE, 0x0FFFF);
++
++ REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
++ SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
++
++ REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
++ SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
++
++ REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
++ SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr +
++ dh_data->zfb_size_in_byte - 1) >> 22);
++ break;
++ case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL:
++ /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
++
++ REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
++ SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
++
++ REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
++ SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
++
++ REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
++ SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr +
++ dh_data->zfb_size_in_byte - 1) >> 22);
++ break;
++ case FRAME_BUFFER_MODE_LOCAL_ONLY:
++ /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
++ REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
++ SDPIF_AGP_BASE, 0);
++
++ REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
++ SDPIF_AGP_BOT, 0X03FFFF);
++
++ REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
++ SDPIF_AGP_TOP, 0);
++ break;
++ default:
++ break;
++ }
++
++ dh_data->dchub_initialzied = true;
++ dh_data->dchub_info_valid = false;
++}
++
+ static void hubp_pg_control(
+ struct dce_hwseq *hws,
+ unsigned int hubp_inst,
+@@ -1615,8 +1915,7 @@ static void program_all_pipe_in_tree(
+ * this OTG. this is done only one time.
+ */
+ /* watermark is for all pipes */
+- pipe_ctx->mi->funcs->program_watermarks(
+- pipe_ctx->mi, &context->bw.dcn.watermarks, ref_clk_mhz);
++ program_watermarks(dc->hwseq, &context->bw.dcn.watermarks, ref_clk_mhz);
+
+ if (dc->public.debug.sanity_checks) {
+ /* pstate stuck check after watermark update */
+@@ -2078,6 +2377,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
+ .apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
+ .set_plane_config = set_plane_config,
+ .update_plane_addr = update_plane_addr,
++ .update_dchub = dcn10_update_dchub,
+ .update_pending_status = dcn10_update_pending_status,
+ .set_input_transfer_func = dcn10_set_input_transfer_func,
+ .set_output_transfer_func = dcn10_set_output_transfer_func,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
+index 1f86295..c56a69b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
+@@ -574,250 +574,6 @@ static void min10_setup(
+ min10_vready_workaround(mem_input, pipe_dest);
+ }
+
+-static uint32_t convert_and_clamp(
+- uint32_t wm_ns,
+- uint32_t refclk_mhz,
+- uint32_t clamp_value)
+-{
+- uint32_t ret_val = 0;
+- ret_val = wm_ns * refclk_mhz;
+- ret_val /= 1000;
+-
+- if (ret_val > clamp_value)
+- ret_val = clamp_value;
+-
+- return ret_val;
+-}
+-
+-static void min10_program_watermarks(
+- struct mem_input *mem_input,
+- struct dcn_watermark_set *watermarks,
+- unsigned int refclk_mhz)
+-{
+- struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input);
+- uint32_t force_en = mem_input->ctx->dc->debug.disable_stutter ? 1 : 0;
+- /*
+- * Need to clamp to max of the register values (i.e. no wrap)
+- * for dcn1, all wm registers are 21-bit wide
+- */
+- uint32_t prog_wm_value;
+-
+- /* Repeat for water mark set A, B, C and D. */
+- /* clock state A */
+- prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns,
+- refclk_mhz, 0x1fffff);
+- REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value);
+-
+- dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS,
+- "URGENCY_WATERMARK_A calculated =%d\n"
+- "HW register value = 0x%x\n",
+- watermarks->a.urgent_ns, prog_wm_value);
+-
+- prog_wm_value = convert_and_clamp(watermarks->a.pte_meta_urgent_ns,
+- refclk_mhz, 0x1fffff);
+- REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A, prog_wm_value);
+- dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS,
+- "PTE_META_URGENCY_WATERMARK_A calculated =%d\n"
+- "HW register value = 0x%x\n",
+- watermarks->a.pte_meta_urgent_ns, prog_wm_value);
+-
+-
+- prog_wm_value = convert_and_clamp(
+- watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns,
+- refclk_mhz, 0x1fffff);
+-
+- REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value);
+- dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS,
+- "SR_ENTER_EXIT_WATERMARK_A calculated =%d\n"
+- "HW register value = 0x%x\n",
+- watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
+-
+-
+- prog_wm_value = convert_and_clamp(
+- watermarks->a.cstate_pstate.cstate_exit_ns,
+- refclk_mhz, 0x1fffff);
+- REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value);
+- dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS,
+- "SR_EXIT_WATERMARK_A calculated =%d\n"
+- "HW register value = 0x%x\n",
+- watermarks->a.cstate_pstate.cstate_exit_ns, prog_wm_value);
+-
+-
+- prog_wm_value = convert_and_clamp(
+- watermarks->a.cstate_pstate.pstate_change_ns,
+- refclk_mhz, 0x1fffff);
+- REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value);
+- dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS,
+- "DRAM_CLK_CHANGE_WATERMARK_A calculated =%d\n"
+- "HW register value = 0x%x\n\n",
+- watermarks->a.cstate_pstate.pstate_change_ns, prog_wm_value);
+-
+-
+- /* clock state B */
+- prog_wm_value = convert_and_clamp(
+- watermarks->b.urgent_ns, refclk_mhz, 0x1fffff);
+- REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, prog_wm_value);
+- dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS,
+- "URGENCY_WATERMARK_B calculated =%d\n"
+- "HW register value = 0x%x\n",
+- watermarks->b.urgent_ns, prog_wm_value);
+-
+-
+- prog_wm_value = convert_and_clamp(
+- watermarks->b.pte_meta_urgent_ns,
+- refclk_mhz, 0x1fffff);
+- REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B, prog_wm_value);
+- dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS,
+- "PTE_META_URGENCY_WATERMARK_B calculated =%d\n"
+- "HW register value = 0x%x\n",
+- watermarks->b.pte_meta_urgent_ns, prog_wm_value);
+-
+-
+- prog_wm_value = convert_and_clamp(
+- watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns,
+- refclk_mhz, 0x1fffff);
+- REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value);
+- dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS,
+- "SR_ENTER_WATERMARK_B calculated =%d\n"
+- "HW register value = 0x%x\n",
+- watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
+-
+-
+- prog_wm_value = convert_and_clamp(
+- watermarks->b.cstate_pstate.cstate_exit_ns,
+- refclk_mhz, 0x1fffff);
+- REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, prog_wm_value);
+- dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS,
+- "SR_EXIT_WATERMARK_B calculated =%d\n"
+- "HW register value = 0x%x\n",
+- watermarks->b.cstate_pstate.cstate_exit_ns, prog_wm_value);
+-
+- prog_wm_value = convert_and_clamp(
+- watermarks->b.cstate_pstate.pstate_change_ns,
+- refclk_mhz, 0x1fffff);
+- REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value);
+- dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS,
+- "DRAM_CLK_CHANGE_WATERMARK_B calculated =%d\n\n"
+- "HW register value = 0x%x\n",
+- watermarks->b.cstate_pstate.pstate_change_ns, prog_wm_value);
+-
+- /* clock state C */
+- prog_wm_value = convert_and_clamp(
+- watermarks->c.urgent_ns, refclk_mhz, 0x1fffff);
+- REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, prog_wm_value);
+- dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS,
+- "URGENCY_WATERMARK_C calculated =%d\n"
+- "HW register value = 0x%x\n",
+- watermarks->c.urgent_ns, prog_wm_value);
+-
+-
+- prog_wm_value = convert_and_clamp(
+- watermarks->c.pte_meta_urgent_ns,
+- refclk_mhz, 0x1fffff);
+- REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C, prog_wm_value);
+- dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS,
+- "PTE_META_URGENCY_WATERMARK_C calculated =%d\n"
+- "HW register value = 0x%x\n",
+- watermarks->c.pte_meta_urgent_ns, prog_wm_value);
+-
+-
+- prog_wm_value = convert_and_clamp(
+- watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns,
+- refclk_mhz, 0x1fffff);
+- REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value);
+- dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS,
+- "SR_ENTER_WATERMARK_C calculated =%d\n"
+- "HW register value = 0x%x\n",
+- watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
+-
+-
+- prog_wm_value = convert_and_clamp(
+- watermarks->c.cstate_pstate.cstate_exit_ns,
+- refclk_mhz, 0x1fffff);
+- REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, prog_wm_value);
+- dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS,
+- "SR_EXIT_WATERMARK_C calculated =%d\n"
+- "HW register value = 0x%x\n",
+- watermarks->c.cstate_pstate.cstate_exit_ns, prog_wm_value);
+-
+-
+- prog_wm_value = convert_and_clamp(
+- watermarks->c.cstate_pstate.pstate_change_ns,
+- refclk_mhz, 0x1fffff);
+- REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value);
+- dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS,
+- "DRAM_CLK_CHANGE_WATERMARK_C calculated =%d\n\n"
+- "HW register value = 0x%x\n",
+- watermarks->c.cstate_pstate.pstate_change_ns, prog_wm_value);
+-
+- /* clock state D */
+- prog_wm_value = convert_and_clamp(
+- watermarks->d.urgent_ns, refclk_mhz, 0x1fffff);
+- REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, prog_wm_value);
+- dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS,
+- "URGENCY_WATERMARK_D calculated =%d\n"
+- "HW register value = 0x%x\n",
+- watermarks->d.urgent_ns, prog_wm_value);
+-
+- prog_wm_value = convert_and_clamp(
+- watermarks->d.pte_meta_urgent_ns,
+- refclk_mhz, 0x1fffff);
+- REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D, prog_wm_value);
+- dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS,
+- "PTE_META_URGENCY_WATERMARK_D calculated =%d\n"
+- "HW register value = 0x%x\n",
+- watermarks->d.pte_meta_urgent_ns, prog_wm_value);
+-
+-
+- prog_wm_value = convert_and_clamp(
+- watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns,
+- refclk_mhz, 0x1fffff);
+- REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value);
+- dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS,
+- "SR_ENTER_WATERMARK_D calculated =%d\n"
+- "HW register value = 0x%x\n",
+- watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
+-
+-
+- prog_wm_value = convert_and_clamp(
+- watermarks->d.cstate_pstate.cstate_exit_ns,
+- refclk_mhz, 0x1fffff);
+- REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, prog_wm_value);
+- dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS,
+- "SR_EXIT_WATERMARK_D calculated =%d\n"
+- "HW register value = 0x%x\n",
+- watermarks->d.cstate_pstate.cstate_exit_ns, prog_wm_value);
+-
+-
+- prog_wm_value = convert_and_clamp(
+- watermarks->d.cstate_pstate.pstate_change_ns,
+- refclk_mhz, 0x1fffff);
+- REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value);
+- dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS,
+- "DRAM_CLK_CHANGE_WATERMARK_D calculated =%d\n"
+- "HW register value = 0x%x\n\n",
+- watermarks->d.cstate_pstate.pstate_change_ns, prog_wm_value);
+-
+- REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
+- DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1);
+- REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
+- DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 0);
+- REG_UPDATE(DCHUBBUB_ARB_SAT_LEVEL,
+- DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz);
+- REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,
+- DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 68);
+-
+- REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL,
+- DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, 0,
+- DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, force_en);
+-
+-#if 0
+- REG_UPDATE_2(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
+- DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, 1,
+- DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1);
+-#endif
+-}
+-
+ static void min10_program_display_marks(
+ struct mem_input *mem_input,
+ struct dce_watermarks nbp,
+@@ -855,63 +611,6 @@ static bool min10_is_flip_pending(struct mem_input *mem_input)
+ return false;
+ }
+
+-static void min10_update_dchub(
+- struct mem_input *mem_input,
+- struct dchub_init_data *dh_data)
+-{
+- struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input);
+- /* TODO: port code from dal2 */
+- switch (dh_data->fb_mode) {
+- case FRAME_BUFFER_MODE_ZFB_ONLY:
+- /*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/
+- REG_UPDATE(DCHUBBUB_SDPIF_FB_TOP,
+- SDPIF_FB_TOP, 0);
+-
+- REG_UPDATE(DCHUBBUB_SDPIF_FB_BASE,
+- SDPIF_FB_BASE, 0x0FFFF);
+-
+- REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
+- SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
+-
+- REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
+- SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
+-
+- REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
+- SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr +
+- dh_data->zfb_size_in_byte - 1) >> 22);
+- break;
+- case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL:
+- /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
+-
+- REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
+- SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
+-
+- REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
+- SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
+-
+- REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
+- SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr +
+- dh_data->zfb_size_in_byte - 1) >> 22);
+- break;
+- case FRAME_BUFFER_MODE_LOCAL_ONLY:
+- /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
+- REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
+- SDPIF_AGP_BASE, 0);
+-
+- REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
+- SDPIF_AGP_BOT, 0X03FFFF);
+-
+- REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
+- SDPIF_AGP_TOP, 0);
+- break;
+- default:
+- break;
+- }
+-
+- dh_data->dchub_initialzied = true;
+- dh_data->dchub_info_valid = false;
+-}
+-
+ struct vm_system_aperture_param {
+ PHYSICAL_ADDRESS_LOC sys_default;
+ PHYSICAL_ADDRESS_LOC sys_low;
+@@ -1114,8 +813,6 @@ static struct mem_input_funcs dcn10_mem_input_funcs = {
+ min10_program_surface_config,
+ .mem_input_is_flip_pending = min10_is_flip_pending,
+ .mem_input_setup = min10_setup,
+- .program_watermarks = min10_program_watermarks,
+- .mem_input_update_dchub = min10_update_dchub,
+ .mem_input_program_pte_vm = min10_program_pte_vm,
+ .set_blank = min10_set_blank,
+ .dcc_control = min10_dcc_control,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
+index 0f4d247..9130f5e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
+@@ -98,30 +98,6 @@
+ SRI(DCN_SURF1_TTU_CNTL0, HUBPREQ, id),\
+ SRI(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),\
+ SRI(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id),\
+- SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\
+- SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A),\
+- SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A),\
+- SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A),\
+- SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A),\
+- SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\
+- SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B),\
+- SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B),\
+- SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B),\
+- SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B),\
+- SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\
+- SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C),\
+- SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C),\
+- SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C),\
+- SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C),\
+- SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\
+- SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D),\
+- SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D),\
+- SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D),\
+- SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D),\
+- SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\
+- SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\
+- SR(DCHUBBUB_ARB_SAT_LEVEL),\
+- SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\
+ /* todo: get these from GVM instead of reading registers ourselves */\
+ MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),\
+ MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),\
+@@ -154,12 +130,8 @@
+ SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, HUBPREQ, id),\
+ SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, HUBPREQ, id),\
+ SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, HUBPREQ, id),\
+- SR(DCHUBBUB_SDPIF_FB_TOP),\
+ SR(DCHUBBUB_SDPIF_FB_BASE),\
+- SR(DCHUBBUB_SDPIF_FB_OFFSET),\
+- SR(DCHUBBUB_SDPIF_AGP_BASE),\
+- SR(DCHUBBUB_SDPIF_AGP_BOT),\
+- SR(DCHUBBUB_SDPIF_AGP_TOP)
++ SR(DCHUBBUB_SDPIF_FB_OFFSET)
+
+ struct dcn_mi_registers {
+ uint32_t DCHUBP_CNTL;
+@@ -248,42 +220,14 @@ struct dcn_mi_registers {
+ uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB;
+ uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR;
+ uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR;
+- uint32_t DCHUBBUB_SDPIF_FB_TOP;
+ uint32_t DCHUBBUB_SDPIF_FB_BASE;
+ uint32_t DCHUBBUB_SDPIF_FB_OFFSET;
+- uint32_t DCHUBBUB_SDPIF_AGP_BASE;
+- uint32_t DCHUBBUB_SDPIF_AGP_BOT;
+- uint32_t DCHUBBUB_SDPIF_AGP_TOP;
+ uint32_t DCN_VM_FB_LOCATION_TOP;
+ uint32_t DCN_VM_FB_LOCATION_BASE;
+ uint32_t DCN_VM_FB_OFFSET;
+ uint32_t DCN_VM_AGP_BASE;
+ uint32_t DCN_VM_AGP_BOT;
+ uint32_t DCN_VM_AGP_TOP;
+- uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A;
+- uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A;
+- uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A;
+- uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A;
+- uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;
+- uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B;
+- uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B;
+- uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B;
+- uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B;
+- uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;
+- uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C;
+- uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C;
+- uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C;
+- uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C;
+- uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;
+- uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D;
+- uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D;
+- uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D;
+- uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D;
+- uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;
+- uint32_t DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL;
+- uint32_t DCHUBBUB_ARB_DRAM_STATE_CNTL;
+- uint32_t DCHUBBUB_ARB_SAT_LEVEL;
+- uint32_t DCHUBBUB_ARB_DF_REQ_OUTSTAND;
+
+ /* GC registers. read only. temporary hack */
+ uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32;
+@@ -418,13 +362,7 @@ struct dcn_mi_registers {
+ MI_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\
+ MI_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\
+ MI_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\
+- MI_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, mask_sh),\
+- MI_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh),\
+- MI_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh),\
+- MI_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, mask_sh),\
+- MI_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, mask_sh),\
+- MI_SF(DCHUBBUB_ARB_SAT_LEVEL, DCHUBBUB_ARB_SAT_LEVEL, mask_sh),\
+- MI_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh)
++ MI_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, mask_sh)
+
+ #define MI_MASK_SH_LIST_DCN10(mask_sh)\
+ MI_MASK_SH_LIST_DCN(mask_sh),\
+@@ -443,12 +381,8 @@ struct dcn_mi_registers {
+ MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mask_sh),\
+ MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mask_sh),\
+ MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mask_sh),\
+- MI_SF(DCHUBBUB_SDPIF_FB_TOP, SDPIF_FB_TOP, mask_sh),\
+ MI_SF(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh),\
+ MI_SF(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh),\
+- MI_SF(DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh),\
+- MI_SF(DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh),\
+- MI_SF(DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh),\
+ MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\
+ MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\
+ MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh),\
+@@ -611,12 +545,6 @@ struct dcn_mi_registers {
+ type AGP_BASE;\
+ type AGP_BOT;\
+ type AGP_TOP;\
+- type DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST;\
+- type DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE;\
+- type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE;\
+- type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE;\
+- type DCHUBBUB_ARB_SAT_LEVEL;\
+- type DCHUBBUB_ARB_MIN_REQ_OUTSTAND;\
+ /* todo: get these from GVM instead of reading registers ourselves */\
+ type PAGE_DIRECTORY_ENTRY_HI32;\
+ type PAGE_DIRECTORY_ENTRY_LO32;\
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
+index 1b7d151..fd3ce74 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
+@@ -75,11 +75,6 @@ struct mem_input {
+
+ struct mem_input_funcs {
+ #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+- void (*program_watermarks)(
+- struct mem_input *mem_input,
+- struct dcn_watermark_set *watermarks,
+- unsigned int refclk_period_ns);
+-
+ void (*mem_input_setup)(
+ struct mem_input *mem_input,
+ struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
+@@ -143,7 +138,7 @@ struct mem_input_funcs {
+ bool (*mem_input_is_flip_pending)(struct mem_input *mem_input);
+
+ void (*mem_input_update_dchub)(struct mem_input *mem_input,
+- struct dchub_init_data *dh_data);
++ struct dchub_init_data *dh_data);
+
+ void (*set_blank)(struct mem_input *mi, bool blank);
+ };
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+index 22aca5a..d865df8 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+@@ -79,6 +79,10 @@ struct hw_sequencer_funcs {
+ const struct core_dc *dc,
+ struct pipe_ctx *pipe_ctx);
+
++ void (*update_dchub)(
++ struct dce_hwseq *hws,
++ struct dchub_init_data *dh_data);
++
+ void (*update_pending_status)(
+ struct pipe_ctx *pipe_ctx);
+
+--
+2.7.4
+