diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0611-drm-amd-display-avoid-disabling-opp-clk-before-hubp-.patch')
-rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0611-drm-amd-display-avoid-disabling-opp-clk-before-hubp-.patch | 163 |
1 files changed, 163 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0611-drm-amd-display-avoid-disabling-opp-clk-before-hubp-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0611-drm-amd-display-avoid-disabling-opp-clk-before-hubp-.patch new file mode 100644 index 00000000..b136ede6 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0611-drm-amd-display-avoid-disabling-opp-clk-before-hubp-.patch @@ -0,0 +1,163 @@ +From d88725a5d91d3e2468738e0e11158b296de4e752 Mon Sep 17 00:00:00 2001 +From: Tony Cheng <tony.cheng@amd.com> +Date: Wed, 12 Jul 2017 11:54:10 -0400 +Subject: [PATCH 0611/4131] drm/amd/display: avoid disabling opp clk before + hubp is blanked. + +Signed-off-by: Tony Cheng <tony.cheng@amd.com> +Reviewed-by: Eric Yang <eric.yang2@amd.com> +Acked-by: Harry Wentland <Harry.Wentland@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 7 +++++++ + .../gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 18 ++++++++++++++---- + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 2 -- + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h | 8 ++------ + 4 files changed, 23 insertions(+), 12 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +index 6985a46..4da9142 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +@@ -141,6 +141,10 @@ + SRII(DPP_CONTROL, DPP_TOP, 1), \ + SRII(DPP_CONTROL, DPP_TOP, 2), \ + SRII(DPP_CONTROL, DPP_TOP, 3), \ ++ SRII(OPP_PIPE_CONTROL, OPP_PIPE, 0), \ ++ SRII(OPP_PIPE_CONTROL, OPP_PIPE, 1), \ ++ SRII(OPP_PIPE_CONTROL, OPP_PIPE, 2), \ ++ SRII(OPP_PIPE_CONTROL, OPP_PIPE, 3), \ + SR(REFCLK_CNTL), \ + SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ + SR(DC_IP_REQUEST_CNTL), \ +@@ -188,6 +192,7 @@ struct dce_hwseq_registers { + uint32_t DCHUBP_CNTL[4]; + uint32_t HUBP_CLK_CNTL[4]; + uint32_t DPP_CONTROL[4]; ++ uint32_t OPP_PIPE_CONTROL[4]; + uint32_t REFCLK_CNTL; + uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL; + uint32_t DC_IP_REQUEST_CNTL; +@@ -282,6 +287,7 @@ struct dce_hwseq_registers { + HWS_SF(HUBP0_, DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh), \ + HWS_SF(HUBP0_, HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh), \ + HWS_SF(DPP_TOP0_, DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \ ++ HWS_SF(OPP_PIPE0_, OPP_PIPE_CONTROL, OPP_PIPE_CLOCK_EN, mask_sh),\ + HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \ + HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ + HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ +@@ -346,6 +352,7 @@ struct dce_hwseq_registers { + type DPP_CLOCK_ENABLE; \ + type DPPCLK_RATE_CONTROL; \ + type DCHUBBUB_GLOBAL_TIMER_ENABLE; \ ++ type OPP_PIPE_CLOCK_EN;\ + type IP_REQUEST_EN; \ + type DOMAIN0_POWER_FORCEON; \ + type DOMAIN0_POWER_GATE; \ +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +index 0e90e6c..18686be 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +@@ -472,9 +472,10 @@ static void reset_front_end( + struct transform *xfm = dc->res_pool->transforms[fe_idx]; + struct mpcc *mpcc = dc->res_pool->mpcc[fe_idx]; + struct timing_generator *tg = dc->res_pool->timing_generators[mpcc->opp_id]; ++ unsigned int opp_id = mpcc->opp_id; + + /*Already reset*/ +- if (mpcc->opp_id == 0xf) ++ if (opp_id == 0xf) + return; + + tg->funcs->lock(tg); +@@ -497,8 +498,12 @@ static void reset_front_end( + + mpcc->funcs->wait_for_idle(mpcc); + +- REG_UPDATE(HUBP_CLK_CNTL[fe_idx], HUBP_CLOCK_ENABLE, 0); +- REG_UPDATE(DPP_CONTROL[fe_idx], DPP_CLOCK_ENABLE, 0); ++ REG_UPDATE(HUBP_CLK_CNTL[fe_idx], ++ HUBP_CLOCK_ENABLE, 0); ++ REG_UPDATE(DPP_CONTROL[fe_idx], ++ DPP_CLOCK_ENABLE, 0); ++ REG_UPDATE(OPP_PIPE_CONTROL[opp_id], ++ OPP_PIPE_CLOCK_EN, 0); + + xfm->funcs->transform_reset(xfm); + +@@ -1211,7 +1216,12 @@ static void dcn10_power_on_fe( + pipe_ctx->pipe_idx); + + /* enable DCFCLK current DCHUB */ +- REG_UPDATE(HUBP_CLK_CNTL[pipe_ctx->pipe_idx], HUBP_CLOCK_ENABLE, 1); ++ REG_UPDATE(HUBP_CLK_CNTL[pipe_ctx->pipe_idx], ++ HUBP_CLOCK_ENABLE, 1); ++ ++ /* make sure OPP_PIPE_CLOCK_EN = 1 */ ++ REG_UPDATE(OPP_PIPE_CONTROL[pipe_ctx->tg->inst], ++ OPP_PIPE_CLOCK_EN, 1); + + if (dc_surface) { + dm_logger_write(dc->ctx->logger, LOG_DC, +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c +index 9875d81..de3341d 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c +@@ -68,14 +68,12 @@ static void set_output_mux(struct dcn10_mpcc *mpcc10, int opp_id, int mpcc_id) + { + ASSERT(mpcc10->base.opp_id == 0xf || opp_id == mpcc10->base.opp_id); + mpcc10->base.opp_id = opp_id; +- REG_UPDATE(OPP_PIPE_CONTROL[opp_id], OPP_PIPE_CLOCK_EN, 1); + REG_SET(MUX[opp_id], 0, MPC_OUT_MUX, mpcc_id); + } + + static void reset_output_mux(struct dcn10_mpcc *mpcc10) + { + REG_SET(MUX[mpcc10->base.opp_id], 0, MPC_OUT_MUX, 0xf); +- REG_UPDATE(OPP_PIPE_CONTROL[mpcc10->base.opp_id], OPP_PIPE_CLOCK_EN, 0); + mpcc10->base.opp_id = 0xf; + } + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h +index 6a90a8b..2985c5d 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h +@@ -33,8 +33,7 @@ + #define MAX_OPP 6 + + #define MPC_COMMON_REG_LIST_DCN1_0(inst) \ +- SRII(MUX, MPC_OUT, inst),\ +- SRII(OPP_PIPE_CONTROL, OPP_PIPE, inst) ++ SRII(MUX, MPC_OUT, inst) + + #define MPCC_COMMON_REG_LIST_DCN1_0(inst) \ + SRI(MPCC_TOP_SEL, MPCC, inst),\ +@@ -56,7 +55,6 @@ struct dcn_mpcc_registers { + uint32_t MPCC_BG_G_Y; + uint32_t MPCC_BG_R_CR; + uint32_t MPCC_BG_B_CB; +- uint32_t OPP_PIPE_CONTROL[MAX_OPP]; + uint32_t MUX[MAX_OPP]; + }; + +@@ -73,8 +71,7 @@ struct dcn_mpcc_registers { + SF(MPCC0_MPCC_BG_G_Y, MPCC_BG_G_Y, mask_sh),\ + SF(MPCC0_MPCC_BG_R_CR, MPCC_BG_R_CR, mask_sh),\ + SF(MPCC0_MPCC_BG_B_CB, MPCC_BG_B_CB, mask_sh),\ +- SF(MPC_OUT0_MUX, MPC_OUT_MUX, mask_sh),\ +- SF(OPP_PIPE0_OPP_PIPE_CONTROL, OPP_PIPE_CLOCK_EN, mask_sh) ++ SF(MPC_OUT0_MUX, MPC_OUT_MUX, mask_sh) + + #define MPCC_REG_FIELD_LIST(type) \ + type MPCC_TOP_SEL;\ +@@ -90,7 +87,6 @@ struct dcn_mpcc_registers { + type MPCC_BG_R_CR;\ + type MPCC_BG_B_CB;\ + type MPC_OUT_MUX;\ +- type OPP_PIPE_CLOCK_EN;\ + + struct dcn_mpcc_shift { + MPCC_REG_FIELD_LIST(uint8_t) +-- +2.7.4 + |