aboutsummaryrefslogtreecommitdiffstats
path: root/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0575-drm-amd-display-set-drr-during-program-timing.patch
diff options
context:
space:
mode:
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0575-drm-amd-display-set-drr-during-program-timing.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0575-drm-amd-display-set-drr-during-program-timing.patch105
1 files changed, 105 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0575-drm-amd-display-set-drr-during-program-timing.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0575-drm-amd-display-set-drr-during-program-timing.patch
new file mode 100644
index 00000000..a2df9b7d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0575-drm-amd-display-set-drr-during-program-timing.patch
@@ -0,0 +1,105 @@
+From 84db045503229dff11a6a1d83af88452e74d4b5d Mon Sep 17 00:00:00 2001
+From: Yongqiang Sun <yongqiang.sun@amd.com>
+Date: Mon, 26 Jun 2017 16:25:10 -0400
+Subject: [PATCH 0575/4131] drm/amd/display: set drr during program timing.
+
+Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Harry Wentland <Harry.Wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../amd/display/dc/dce110/dce110_timing_generator.c | 21 +++++++++++++++++++++
+ .../amd/display/dc/dce120/dce120_timing_generator.c | 19 ++++++++++++++++---
+ .../amd/display/dc/dcn10/dcn10_timing_generator.c | 8 ++++++++
+ 3 files changed, 45 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
+index ec59927..7f93d6d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
+@@ -629,6 +629,27 @@ void dce110_timing_generator_program_blanking(
+ CRTC_V_TOTAL);
+ dm_write_reg(ctx, addr, value);
+
++ /* In case of V_TOTAL_CONTROL is on, make sure V_TOTAL_MAX and
++ * V_TOTAL_MIN are equal to V_TOTAL.
++ */
++ addr = CRTC_REG(mmCRTC_V_TOTAL_MAX);
++ value = dm_read_reg(ctx, addr);
++ set_reg_field_value(
++ value,
++ timing->v_total - 1,
++ CRTC_V_TOTAL_MAX,
++ CRTC_V_TOTAL_MAX);
++ dm_write_reg(ctx, addr, value);
++
++ addr = CRTC_REG(mmCRTC_V_TOTAL_MIN);
++ value = dm_read_reg(ctx, addr);
++ set_reg_field_value(
++ value,
++ timing->v_total - 1,
++ CRTC_V_TOTAL_MIN,
++ CRTC_V_TOTAL_MIN);
++ dm_write_reg(ctx, addr, value);
++
+ addr = CRTC_REG(mmCRTC_H_BLANK_START_END);
+ value = dm_read_reg(ctx, addr);
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+index 03b21e9..58a070d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+@@ -441,15 +441,28 @@ void dce120_timing_generator_program_blanking(
+ struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
+
+ CRTC_REG_UPDATE(
+- CRTC0_CRTC_H_TOTAL,
+- CRTC_H_TOTAL,
+- timing->h_total - 1);
++ CRTC0_CRTC_H_TOTAL,
++ CRTC_H_TOTAL,
++ timing->h_total - 1);
+
+ CRTC_REG_UPDATE(
+ CRTC0_CRTC_V_TOTAL,
+ CRTC_V_TOTAL,
+ timing->v_total - 1);
+
++ /* In case of V_TOTAL_CONTROL is on, make sure V_TOTAL_MAX and
++ * V_TOTAL_MIN are equal to V_TOTAL.
++ */
++ CRTC_REG_UPDATE(
++ CRTC0_CRTC_V_TOTAL_MAX,
++ CRTC_V_TOTAL_MAX,
++ timing->v_total - 1);
++
++ CRTC_REG_UPDATE(
++ CRTC0_CRTC_V_TOTAL_MIN,
++ CRTC_V_TOTAL_MIN,
++ timing->v_total - 1);
++
+ tmp1 = timing->h_total -
+ (h_sync_start + timing->h_border_left);
+ tmp2 = tmp1 + timing->h_addressable +
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
+index 5927478..e1899f5 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
+@@ -177,6 +177,14 @@ static void tgn10_program_timing(
+ REG_SET(OTG_V_TOTAL, 0,
+ OTG_V_TOTAL, v_total);
+
++ /* In case of V_TOTAL_CONTROL is on, make sure OTG_V_TOTAL_MAX and
++ * OTG_V_TOTAL_MIN are equal to V_TOTAL.
++ */
++ REG_SET(OTG_V_TOTAL_MAX, 0,
++ OTG_V_TOTAL_MAX, v_total);
++ REG_SET(OTG_V_TOTAL_MIN, 0,
++ OTG_V_TOTAL_MIN, v_total);
++
+ /* v_sync_start = 0, v_sync_end = v_sync_width */
+ v_sync_end = patched_crtc_timing.v_sync_width * interlace_factor;
+
+--
+2.7.4
+