diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0290-drm-amd-display-support-PHY-compliance-automation-fo.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0290-drm-amd-display-support-PHY-compliance-automation-fo.patch | 205 |
1 files changed, 205 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0290-drm-amd-display-support-PHY-compliance-automation-fo.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0290-drm-amd-display-support-PHY-compliance-automation-fo.patch new file mode 100644 index 00000000..ea0b466c --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0290-drm-amd-display-support-PHY-compliance-automation-fo.patch @@ -0,0 +1,205 @@ +From 1ea6a40912ccf8a3e78c3f83ee1a359ef604d7ac Mon Sep 17 00:00:00 2001 +From: Tony Cheng <tony.cheng@amd.com> +Date: Tue, 14 Mar 2017 19:16:36 -0400 +Subject: [PATCH 0290/4131] drm/amd/display: support PHY compliance automation + for CP2520 pattern 1/2/3 + +Signed-off-by: Tony Cheng <tony.cheng@amd.com> +Acked-by: Harry Wentland <Harry.Wentland@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 55 ++++++++++++---------- + .../gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 17 +++++-- + drivers/gpu/drm/amd/display/include/dpcd_defs.h | 4 +- + .../drm/amd/display/include/link_service_types.h | 11 +++-- + 4 files changed, 53 insertions(+), 34 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +index ef80473..d04cad2 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +@@ -1599,19 +1599,25 @@ static void dp_test_send_phy_test_pattern(struct core_link *link) + switch (dpcd_test_pattern.bits.PATTERN) { + case PHY_TEST_PATTERN_D10_2: + test_pattern = DP_TEST_PATTERN_D102; +- break; ++ break; + case PHY_TEST_PATTERN_SYMBOL_ERROR: + test_pattern = DP_TEST_PATTERN_SYMBOL_ERROR; +- break; ++ break; + case PHY_TEST_PATTERN_PRBS7: + test_pattern = DP_TEST_PATTERN_PRBS7; +- break; ++ break; + case PHY_TEST_PATTERN_80BIT_CUSTOM: + test_pattern = DP_TEST_PATTERN_80BIT_CUSTOM; +- break; +- case PHY_TEST_PATTERN_HBR2_COMPLIANCE_EYE: +- test_pattern = DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE; +- break; ++ break; ++ case PHY_TEST_PATTERN_CP2520_1: ++ test_pattern = DP_TEST_PATTERN_CP2520_1; ++ break; ++ case PHY_TEST_PATTERN_CP2520_2: ++ test_pattern = DP_TEST_PATTERN_CP2520_2; ++ break; ++ case PHY_TEST_PATTERN_CP2520_3: ++ test_pattern = DP_TEST_PATTERN_CP2520_3; ++ break; + default: + test_pattern = DP_TEST_PATTERN_VIDEO_MODE; + break; +@@ -2202,16 +2208,9 @@ void dc_link_dp_disable_hpd(const struct dc_link *link) + + static bool is_dp_phy_pattern(enum dp_test_pattern test_pattern) + { +- if (test_pattern == DP_TEST_PATTERN_D102 || +- test_pattern == DP_TEST_PATTERN_SYMBOL_ERROR || +- test_pattern == DP_TEST_PATTERN_PRBS7 || +- test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM || +- test_pattern == DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE || +- test_pattern == DP_TEST_PATTERN_TRAINING_PATTERN1 || +- test_pattern == DP_TEST_PATTERN_TRAINING_PATTERN2 || +- test_pattern == DP_TEST_PATTERN_TRAINING_PATTERN3 || +- test_pattern == DP_TEST_PATTERN_TRAINING_PATTERN4 || +- test_pattern == DP_TEST_PATTERN_VIDEO_MODE) ++ if ((DP_TEST_PATTERN_PHY_PATTERN_BEGIN <= test_pattern && ++ test_pattern <= DP_TEST_PATTERN_PHY_PATTERN_END) || ++ test_pattern == DP_TEST_PATTERN_VIDEO_MODE) + return true; + else + return false; +@@ -2377,22 +2376,28 @@ bool dc_link_dp_set_test_pattern( + switch (test_pattern) { + case DP_TEST_PATTERN_VIDEO_MODE: + pattern = PHY_TEST_PATTERN_NONE; +- break; ++ break; + case DP_TEST_PATTERN_D102: + pattern = PHY_TEST_PATTERN_D10_2; +- break; ++ break; + case DP_TEST_PATTERN_SYMBOL_ERROR: + pattern = PHY_TEST_PATTERN_SYMBOL_ERROR; +- break; ++ break; + case DP_TEST_PATTERN_PRBS7: + pattern = PHY_TEST_PATTERN_PRBS7; +- break; ++ break; + case DP_TEST_PATTERN_80BIT_CUSTOM: + pattern = PHY_TEST_PATTERN_80BIT_CUSTOM; +- break; +- case DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE: +- pattern = PHY_TEST_PATTERN_HBR2_COMPLIANCE_EYE; +- break; ++ break; ++ case DP_TEST_PATTERN_CP2520_1: ++ pattern = PHY_TEST_PATTERN_CP2520_1; ++ break; ++ case DP_TEST_PATTERN_CP2520_2: ++ pattern = PHY_TEST_PATTERN_CP2520_2; ++ break; ++ case DP_TEST_PATTERN_CP2520_3: ++ pattern = PHY_TEST_PATTERN_CP2520_3; ++ break; + default: + return false; + } +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +index 65cc64a..ed46e9a 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +@@ -376,7 +376,8 @@ static void set_dp_phy_pattern_80bit_custom( + } + + static void set_dp_phy_pattern_hbr2_compliance_cp2520_2( +- struct dce110_link_encoder *enc110) ++ struct dce110_link_encoder *enc110, ++ unsigned int cp2520_pattern) + { + + /* previously there is a register DP_HBR2_EYE_PATTERN +@@ -408,10 +409,13 @@ static void set_dp_phy_pattern_hbr2_compliance_cp2520_2( + /* swap every BS with SR */ + REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0); + +- /* select cp2520 pattern 2 */ ++ /* select cp2520 patterns */ + if (REG(DP_DPHY_HBR2_PATTERN_CONTROL)) + REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL, +- DP_DPHY_HBR2_PATTERN_CONTROL, 0x2); ++ DP_DPHY_HBR2_PATTERN_CONTROL, cp2520_pattern); ++ else ++ /* pre-DCE11 can only generate CP2520 pattern 2 */ ++ ASSERT(cp2520_pattern == 2); + + /* set link training complete */ + set_link_training_complete(enc110, true); +@@ -1395,8 +1399,11 @@ void dce110_link_encoder_dp_set_phy_pattern( + set_dp_phy_pattern_80bit_custom( + enc110, param->custom_pattern); + break; +- case DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE: +- set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110); ++ case DP_TEST_PATTERN_CP2520_1: ++ set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 1); ++ break; ++ case DP_TEST_PATTERN_CP2520_2: ++ set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 2); + break; + case DP_TEST_PATTERN_VIDEO_MODE: { + set_dp_phy_pattern_passthrough_mode( +diff --git a/drivers/gpu/drm/amd/display/include/dpcd_defs.h b/drivers/gpu/drm/amd/display/include/dpcd_defs.h +index 2dca4a4..482f8b2 100644 +--- a/drivers/gpu/drm/amd/display/include/dpcd_defs.h ++++ b/drivers/gpu/drm/amd/display/include/dpcd_defs.h +@@ -74,7 +74,9 @@ enum dpcd_phy_test_patterns { + PHY_TEST_PATTERN_SYMBOL_ERROR, + PHY_TEST_PATTERN_PRBS7, + PHY_TEST_PATTERN_80BIT_CUSTOM,/* For DP1.2 only */ +- PHY_TEST_PATTERN_HBR2_COMPLIANCE_EYE/* For DP1.2 only */ ++ PHY_TEST_PATTERN_CP2520_1, ++ PHY_TEST_PATTERN_CP2520_2, ++ PHY_TEST_PATTERN_CP2520_3, /* same as TPS4 */ + }; + + enum dpcd_test_dyn_range { +diff --git a/drivers/gpu/drm/amd/display/include/link_service_types.h b/drivers/gpu/drm/amd/display/include/link_service_types.h +index 479e5ff..b232601 100644 +--- a/drivers/gpu/drm/amd/display/include/link_service_types.h ++++ b/drivers/gpu/drm/amd/display/include/link_service_types.h +@@ -75,19 +75,24 @@ enum dp_test_pattern { + /* Input data is pass through Scrambler + * and 8b10b Encoder straight to output*/ + DP_TEST_PATTERN_VIDEO_MODE = 0, ++ + /* phy test patterns*/ +- DP_TEST_PATTERN_D102, ++ DP_TEST_PATTERN_PHY_PATTERN_BEGIN, ++ DP_TEST_PATTERN_D102 = DP_TEST_PATTERN_PHY_PATTERN_BEGIN, + DP_TEST_PATTERN_SYMBOL_ERROR, + DP_TEST_PATTERN_PRBS7, +- + DP_TEST_PATTERN_80BIT_CUSTOM, +- DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE, ++ DP_TEST_PATTERN_CP2520_1, ++ DP_TEST_PATTERN_CP2520_2, ++ DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE = DP_TEST_PATTERN_CP2520_2, + + /* Link Training Patterns */ + DP_TEST_PATTERN_TRAINING_PATTERN1, + DP_TEST_PATTERN_TRAINING_PATTERN2, + DP_TEST_PATTERN_TRAINING_PATTERN3, + DP_TEST_PATTERN_TRAINING_PATTERN4, ++ DP_TEST_PATTERN_CP2520_3 = DP_TEST_PATTERN_TRAINING_PATTERN4, ++ DP_TEST_PATTERN_PHY_PATTERN_END = DP_TEST_PATTERN_TRAINING_PATTERN4, + + /* link test patterns*/ + DP_TEST_PATTERN_COLOR_SQUARES, +-- +2.7.4 + |