diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0247-drm-amd-display-freesync-pipe-split-VTotal_Min_Mask-.patch')
-rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0247-drm-amd-display-freesync-pipe-split-VTotal_Min_Mask-.patch | 246 |
1 files changed, 246 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0247-drm-amd-display-freesync-pipe-split-VTotal_Min_Mask-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0247-drm-amd-display-freesync-pipe-split-VTotal_Min_Mask-.patch new file mode 100644 index 00000000..ca501b00 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0247-drm-amd-display-freesync-pipe-split-VTotal_Min_Mask-.patch @@ -0,0 +1,246 @@ +From c2816a298576728aa596af169250bc7d9b16db2c Mon Sep 17 00:00:00 2001 +From: Charlene Liu <charlene.liu@amd.com> +Date: Tue, 28 Feb 2017 15:23:38 -0500 +Subject: [PATCH 0247/4131] drm/amd/display: freesync pipe split + :VTotal_Min_Mask for Hflip/lock. + +Signed-off-by: Charlene Liu <charlene.liu@amd.com> +Acked-by: Harry Wentland <Harry.Wentland@amd.com> +Reviewed-by: Jordan Lazare <Jordan.Lazare@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/display/dc/core/dc.c | 40 +++++++++++++++------- + drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c | 21 +++++++----- + drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 15 ++------ + drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 20 ++++++++--- + .../drm/amd/display/include/hw_sequencer_types.h | 1 + + 5 files changed, 59 insertions(+), 38 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c +index 852932a..66a5b27 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c +@@ -1178,6 +1178,7 @@ void dc_update_surfaces_for_stream(struct dc *dc, + + enum surface_update_type update_type; + const struct dc_stream_status *stream_status; ++ unsigned int lock_mask = 0; + + stream_status = dc_stream_get_status(dc_stream); + ASSERT(stream_status); +@@ -1315,21 +1316,38 @@ void dc_update_surfaces_for_stream(struct dc *dc, + + for (j = 0; j < context->res_ctx.pool->pipe_count; j++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; ++ if (pipe_ctx->surface != surface) ++ continue; ++ /*lock all the MCPP if blnd is enable for DRR*/ ++ if ((update_type == UPDATE_TYPE_FAST && ++ (dc_stream->freesync_ctx.enabled == true && ++ surface_count != context->res_ctx.pool->pipe_count)) && ++ !pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) { ++ lock_mask = PIPE_LOCK_CONTROL_MPCC_ADDR; ++ core_dc->hwss.pipe_control_lock( ++ core_dc, ++ pipe_ctx, ++ lock_mask, ++ true); ++ } ++ } ++ for (j = 0; j < context->res_ctx.pool->pipe_count; j++) { ++ struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; + struct pipe_ctx *cur_pipe_ctx; + bool is_new_pipe_surface = true; + + if (pipe_ctx->surface != surface) + continue; +- + if (update_type != UPDATE_TYPE_FAST && + !pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) { +- core_dc->hwss.pipe_control_lock( +- core_dc->hwseq, +- pipe_ctx->pipe_idx, +- PIPE_LOCK_CONTROL_GRAPHICS | ++ lock_mask = PIPE_LOCK_CONTROL_GRAPHICS | + PIPE_LOCK_CONTROL_SCL | + PIPE_LOCK_CONTROL_BLENDER | +- PIPE_LOCK_CONTROL_MODE, ++ PIPE_LOCK_CONTROL_MODE; ++ core_dc->hwss.pipe_control_lock( ++ core_dc, ++ pipe_ctx, ++ lock_mask, + true); + } + +@@ -1371,7 +1389,7 @@ void dc_update_surfaces_for_stream(struct dc *dc, + } + } + +- if (update_type == UPDATE_TYPE_FAST) ++ if (update_type == UPDATE_TYPE_FAST && (lock_mask == 0)) + return; + + for (i = context->res_ctx.pool->pipe_count - 1; i >= 0; i--) { +@@ -1381,11 +1399,9 @@ void dc_update_surfaces_for_stream(struct dc *dc, + if (updates[j].surface == &pipe_ctx->surface->public) { + if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) { + core_dc->hwss.pipe_control_lock( +- core_dc->hwseq, +- pipe_ctx->pipe_idx, +- PIPE_LOCK_CONTROL_GRAPHICS | +- PIPE_LOCK_CONTROL_SCL | +- PIPE_LOCK_CONTROL_BLENDER, ++ core_dc, ++ pipe_ctx, ++ lock_mask, + false); + } + break; +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c +index 8eb7556..1e1d60a 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c +@@ -26,6 +26,7 @@ + #include "dce_hwseq.h" + #include "reg_helper.h" + #include "hw_sequencer.h" ++#include "core_dc.h" + + #define CTX \ + hws->ctx +@@ -43,15 +44,17 @@ void dce_enable_fe_clock(struct dce_hwseq *hws, + DCFE_CLOCK_ENABLE, enable); + } + +-void dce_pipe_control_lock(struct dce_hwseq *hws, +- unsigned int blnd_inst, ++void dce_pipe_control_lock(struct core_dc *dc, ++ struct pipe_ctx *pipe, + enum pipe_lock_control control_mask, + bool lock) + { + uint32_t lock_val = lock ? 1 : 0; +- uint32_t dcp_grph, scl, blnd, update_lock_mode; +- +- uint32_t val = REG_GET_4(BLND_V_UPDATE_LOCK[blnd_inst], ++ uint32_t dcp_grph, scl, blnd, update_lock_mode, val; ++ struct dce_hwseq *hws = dc->hwseq; ++ if (control_mask & PIPE_LOCK_CONTROL_MPCC_ADDR) ++ return; ++ val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->pipe_idx], + BLND_DCP_GRPH_V_UPDATE_LOCK, &dcp_grph, + BLND_SCL_V_UPDATE_LOCK, &scl, + BLND_BLND_V_UPDATE_LOCK, &blnd, +@@ -70,19 +73,19 @@ void dce_pipe_control_lock(struct dce_hwseq *hws, + update_lock_mode = lock_val; + + +- REG_SET_2(BLND_V_UPDATE_LOCK[blnd_inst], val, ++ REG_SET_2(BLND_V_UPDATE_LOCK[pipe->pipe_idx], val, + BLND_DCP_GRPH_V_UPDATE_LOCK, dcp_grph, + BLND_SCL_V_UPDATE_LOCK, scl); + + if (hws->masks->BLND_BLND_V_UPDATE_LOCK != 0) +- REG_SET_2(BLND_V_UPDATE_LOCK[blnd_inst], val, ++ REG_SET_2(BLND_V_UPDATE_LOCK[pipe->pipe_idx], val, + BLND_BLND_V_UPDATE_LOCK, blnd, + BLND_V_UPDATE_LOCK_MODE, update_lock_mode); + + if (hws->wa.blnd_crtc_trigger) { + if (!lock && (control_mask & PIPE_LOCK_CONTROL_BLENDER)) { +- uint32_t value = REG_READ(CRTC_H_BLANK_START_END[blnd_inst]); +- REG_WRITE(CRTC_H_BLANK_START_END[blnd_inst], value); ++ uint32_t value = REG_READ(CRTC_H_BLANK_START_END[pipe->pipe_idx]); ++ REG_WRITE(CRTC_H_BLANK_START_END[pipe->pipe_idx], value); + } + } + } +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +index 4af8d56..9ef6184 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +@@ -212,17 +212,6 @@ struct dce_hwseq_mask { + HWSEQ_REG_FIED_LIST(uint32_t) + }; + +-struct dce_hwseq_wa { +- bool blnd_crtc_trigger; +-}; +- +-struct dce_hwseq { +- struct dc_context *ctx; +- const struct dce_hwseq_registers *regs; +- const struct dce_hwseq_shift *shifts; +- const struct dce_hwseq_mask *masks; +- struct dce_hwseq_wa wa; +-}; + + enum blnd_mode { + BLND_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */ +@@ -233,8 +222,8 @@ enum blnd_mode { + void dce_enable_fe_clock(struct dce_hwseq *hwss, + unsigned int inst, bool enable); + +-void dce_pipe_control_lock(struct dce_hwseq *hws, +- unsigned int blnd_inst, ++void dce_pipe_control_lock(struct core_dc *dc, ++ struct pipe_ctx *pipe, + enum pipe_lock_control control_mask, + bool lock); + +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +index 7b780c6..a902de5 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +@@ -38,10 +38,22 @@ enum pipe_lock_control { + PIPE_LOCK_CONTROL_GRAPHICS = 1 << 0, + PIPE_LOCK_CONTROL_BLENDER = 1 << 1, + PIPE_LOCK_CONTROL_SCL = 1 << 2, +- PIPE_LOCK_CONTROL_MODE = 1 << 3 ++ PIPE_LOCK_CONTROL_MODE = 1 << 3, ++ PIPE_LOCK_CONTROL_MPCC_ADDR = 1 << 4 ++}; ++ ++struct dce_hwseq_wa { ++ bool blnd_crtc_trigger; ++}; ++ ++struct dce_hwseq { ++ struct dc_context *ctx; ++ const struct dce_hwseq_registers *regs; ++ const struct dce_hwseq_shift *shifts; ++ const struct dce_hwseq_mask *masks; ++ struct dce_hwseq_wa wa; + }; + +-struct dce_hwseq; + + struct hw_sequencer_funcs { + +@@ -115,8 +127,8 @@ struct hw_sequencer_funcs { + struct dc_link_settings *link_settings); + + void (*pipe_control_lock)( +- struct dce_hwseq *hwseq, +- unsigned int blnd_inst, ++ struct core_dc *dc, ++ struct pipe_ctx *pipe, + enum pipe_lock_control control_mask, + bool lock); + +diff --git a/drivers/gpu/drm/amd/display/include/hw_sequencer_types.h b/drivers/gpu/drm/amd/display/include/hw_sequencer_types.h +index 6f0475c..065a91a 100644 +--- a/drivers/gpu/drm/amd/display/include/hw_sequencer_types.h ++++ b/drivers/gpu/drm/amd/display/include/hw_sequencer_types.h +@@ -38,6 +38,7 @@ struct drr_params { + /* defines the maximum possible vertical dimension of display timing + * for CRTC as supported by the panel */ + uint32_t vertical_total_max; ++ bool immediate_flip; + }; + + #endif +-- +2.7.4 + |