diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0219-drm-amd-display-Don-t-attempt-to-program-missing-reg.patch')
-rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0219-drm-amd-display-Don-t-attempt-to-program-missing-reg.patch | 107 |
1 files changed, 107 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0219-drm-amd-display-Don-t-attempt-to-program-missing-reg.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0219-drm-amd-display-Don-t-attempt-to-program-missing-reg.patch new file mode 100644 index 00000000..22672923 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0219-drm-amd-display-Don-t-attempt-to-program-missing-reg.patch @@ -0,0 +1,107 @@ +From 7d0233a8e3dca32a8d6358434943dcc62d1fab24 Mon Sep 17 00:00:00 2001 +From: Jordan Lazare <Jordan.Lazare@amd.com> +Date: Tue, 14 Feb 2017 18:20:35 -0500 +Subject: [PATCH 0219/4131] drm/amd/display: Don't attempt to program missing + register fields on DCE8 + +When moving to a common dce/ infrastructure for all asics, some register fields +do not exist in DCE8, and cause ASSERTS and debug spam. + +Instead, check to see whether a register field mask is valid before attempting +to program the register field + +Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c | 29 ++++++++++++++-------- + drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 12 ++++++--- + 2 files changed, 28 insertions(+), 13 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c +index 0eee135..8eb7556 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c +@@ -69,17 +69,22 @@ void dce_pipe_control_lock(struct dce_hwseq *hws, + if (control_mask & PIPE_LOCK_CONTROL_MODE) + update_lock_mode = lock_val; + +- REG_SET_4(BLND_V_UPDATE_LOCK[blnd_inst], val, ++ ++ REG_SET_2(BLND_V_UPDATE_LOCK[blnd_inst], val, + BLND_DCP_GRPH_V_UPDATE_LOCK, dcp_grph, +- BLND_SCL_V_UPDATE_LOCK, scl, +- BLND_BLND_V_UPDATE_LOCK, blnd, +- BLND_V_UPDATE_LOCK_MODE, update_lock_mode); ++ BLND_SCL_V_UPDATE_LOCK, scl); ++ ++ if (hws->masks->BLND_BLND_V_UPDATE_LOCK != 0) ++ REG_SET_2(BLND_V_UPDATE_LOCK[blnd_inst], val, ++ BLND_BLND_V_UPDATE_LOCK, blnd, ++ BLND_V_UPDATE_LOCK_MODE, update_lock_mode); + +- if (hws->wa.blnd_crtc_trigger) ++ if (hws->wa.blnd_crtc_trigger) { + if (!lock && (control_mask & PIPE_LOCK_CONTROL_BLENDER)) { + uint32_t value = REG_READ(CRTC_H_BLANK_START_END[blnd_inst]); + REG_WRITE(CRTC_H_BLANK_START_END[blnd_inst], value); + } ++ } + } + + void dce_set_blender_mode(struct dce_hwseq *hws, +@@ -111,11 +116,15 @@ void dce_set_blender_mode(struct dce_hwseq *hws, + break; + } + +- REG_UPDATE_4(BLND_CONTROL[blnd_inst], +- BLND_FEEDTHROUGH_EN, feedthrough, +- BLND_ALPHA_MODE, alpha_mode, +- BLND_MODE, blnd_mode, +- BLND_MULTIPLIED_MODE, multiplied_mode); ++ REG_UPDATE(BLND_CONTROL[blnd_inst], ++ BLND_MODE, blnd_mode); ++ ++ if (hws->masks->BLND_ALPHA_MODE != 0) { ++ REG_UPDATE_3(BLND_CONTROL[blnd_inst], ++ BLND_FEEDTHROUGH_EN, feedthrough, ++ BLND_ALPHA_MODE, alpha_mode, ++ BLND_MULTIPLIED_MODE, multiplied_mode); ++ } + } + + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c +index 50a6a25..d8ffbff 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c +@@ -87,7 +87,10 @@ static bool setup_scaling_configuration( + + if (data->taps.h_taps + data->taps.v_taps <= 2) { + /* Set bypass */ +- REG_UPDATE_2(SCL_MODE, SCL_MODE, 0, SCL_PSCL_EN, 0); ++ if (xfm_dce->xfm_mask->SCL_PSCL_EN != 0) ++ REG_UPDATE_2(SCL_MODE, SCL_MODE, 0, SCL_PSCL_EN, 0); ++ else ++ REG_UPDATE(SCL_MODE, SCL_MODE, 0); + return false; + } + +@@ -96,9 +99,12 @@ static bool setup_scaling_configuration( + SCL_V_NUM_OF_TAPS, data->taps.v_taps - 1); + + if (data->format <= PIXEL_FORMAT_GRPH_END) +- REG_UPDATE_2(SCL_MODE, SCL_MODE, 1, SCL_PSCL_EN, 1); ++ REG_UPDATE(SCL_MODE, SCL_MODE, 1); + else +- REG_UPDATE_2(SCL_MODE, SCL_MODE, 2, SCL_PSCL_EN, 1); ++ REG_UPDATE(SCL_MODE, SCL_MODE, 2); ++ ++ if (xfm_dce->xfm_mask->SCL_PSCL_EN != 0) ++ REG_UPDATE(SCL_MODE, SCL_PSCL_EN, 1); + + /* 1 - Replace out of bound pixels with edge */ + REG_SET(SCL_CONTROL, 0, SCL_BOUNDARY_MODE, 1); +-- +2.7.4 + |